Applied Materials : New Methods of Defect Inspection and Review Improve Yield of Advanced Chips

As the industry moves to sub-1Xnm nodes and adopts new architectures with higher aspect ratio (HAR) features and multiple patterning steps, the ability to detect and identify defects to improve yield is becoming increasingly difficult. First, as defects of interest (DOI) shrink along with feature sizes, they are getting harder to detect and image. In addition, the detection signal of a defect is getting more and more immersed in the noise of false defects and the challenge of separating these from true issues is growing. Also, more complex defect analysis is required for DOI with 3D morphology and for previous layer DOI.

Defect reduction is an iterative process that involves detection of defects by inspection and review (I&R) tools, classification of defects, identification of the source, optimization of the process to eliminate defect formation and finally monitoring for process excursions. In advanced nodes, where device-killing defects are becoming smaller than the pattern variation/process variability, extracting DOI with minimal false identification is critical for accurate yield prediction and root cause analysis. However, inline I&R techniques using defect review scanning electron microscopy (DR-SEM) are facing challenges to get enough signal-to-noise ratio of the DOI.

Figure 1: (A) Schematic showing that as the design rules shrink, the DOI signal becomes immersed in noise. (B) Schematic of a field of view (FOV) for DR-SEM, where the Process Variations mask the true DOI. The smaller the FOV, the less likely it is to have false re-detection and high sensitivity [1].

High-resolution images acquired by the DR-SEM are needed for defect classification. The DR-SEM navigates to each defect location reported by the inspection tools and grabs SEM images of a certain field of view (FOV). The FOV required for navigation to the defect's location is determined by two factors: defect visibility in the SEM image, which forces small pixel size, and navigation errors that must be compensated with adequately large FOV. If the FOV is not large enough, the defect is not guaranteed to appear in the acquired image, especially when running identical steps across a fleet of SEM tools.

After navigating to the desired location, the DR-SEM tool automatically performs defect re-detection by comparing the reported region to a reference region in a neighboring die on the wafer. But noise from process variation or multiple defects in the region can mask the true DOI in the same FOV. As defects get smaller, the FOV used by the DR-SEM for defect re-detection in 2Xnm node technologies is now too large for sub 1Xnm nodes. The FOV used should be large enough to cover the defect distribution, but not too big to compromise the sensitivity of re-detection and miss the DOI. The goal is to review the wafer in the smallest FOV possible with small pixel size and high throughput, and also achieve 100% capture rate of the real defects present.

In a technical paper co-written by Applied Materials and GLOBALFOUNDRIES titled, 'SEM Imaging and Automated Defect Analysis at Advanced Technology Nodes' presented at the recent ASMC (Advanced Semiconductor Manufacturing Conference) [1], we discuss a new DR-SEM approach to I&R. By implementing the practice of wafer alignment to computer-aided design coordinates in the I&R loop, we found reporting defect locations this way eliminates tool/user discrepancy and facilitates robust DOI searching in much smaller FOVs. Further, the implementation of Automated Defect Analysis using techniques such as see-through imaging, quantitative materials analysis and tilt imaging on select DOI subsets allows for root cause analysis and improved classification of defects.

For further information on this topic, please contact me at Abhinav_Jain@amat.com.

[1] A. Jain, J.G. Sheridan, R. Xing, F. Levitov, S. Yasharzade, H. Nguyen, 'SEM Imaging and Automated Defect Analysis at Advanced Technology Nodes: Defect Inspection', Proceedings of SEMI Advanced Semiconductor Manufacturing Conference (ASMC), Saratoga Springs, NY, 2017, to be published.