Cadence Expands Proven Ethernet IP Offering with 40/100 Gigabit Ethernet Solution

Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced 40/100 Gigabit Ethernet (GbE) media access controller (MAC) and physical coding sub-layer (PCS) IP cores that enable the rapid deployment of SoCs for networking and high-performance computing. With more than 50 tape-outs of Ethernet designs spanning from 1 GbE up to 40 GbE, Cadence offers both the design IP and integration support required to ensure silicon success. Cadence's Ethernet solutions include unique capabilities in verification IP (VIP), emulation, virtual prototyping and silicon-package-board co-design.

"For over a decade, Cadence has worked with the industry's largest semiconductor companies to design leading Ethernet SoCs for networking and high-performance computing applications, while also helping drive the development of Ethernet standards," said Vishal Kapoor, vice president, product marketing, SoC Realization at Cadence. "As large scale data centers begin their transition to 40/100 GbE over the next three years, we want to empower our customers with the tools they need to take advantage of the anticipated rapid growth in the ultra high-speed Gigabit Ethernet market."

The Dell'Oro Group forecasts robust growth in 40 Gigabit Ethernet and 100 Gigabit Ethernet with the market for these combined technologies expected to exceed $3B by 2016.

The Cadence 40/100 GbE MAC and PCS IP cores support the latest version of the IEEE 802.3ba-2010 Ethernet specification and sub-specifications including Energy Efficient Ethernet for power savings during idle time. The IP includes a host of configurable features such as Ethernet address match logic and frame- and priority-based flow control mechanisms for application-based customization of traffic control. In addition, a programmable inter-frame gap feature enables precise packet flow control to avoid equipment overload. Finally, the IP provides comprehensive monitoring features including error/status word for each frame that is transmitted and received; remote monitoring (RMON) and management information base (MIB) support. The 40/100 GbE MAC IP supports Gigabit media independent interfaces (XLGMII and CGMII) for connection to the attached PHY layer device, whereas the 40/100 GbE PCS IP supports integration with four/ten 10 Gigabit SerDes.

Availability
The design IP, including MAC and PCS, as well VIP, emulation and virtual prototyping support, are available immediately.

Cadence Expands Proven Ethernet IP Offering with 40/100 Gigabit Ethernet Solution

Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced 40/100 Gigabit Ethernet (GbE) media access controller (MAC) and physical coding sub-layer (PCS) IP cores that enable the rapid deployment of SoCs for networking and high-performance computing. With more than 50 tape-outs of Ethernet designs spanning from 1 GbE up to 40 GbE, Cadence offers both the design IP and integration support required to ensure silicon success. Cadence's Ethernet solutions include unique capabilities in verification IP (VIP), emulation, virtual prototyping and silicon-package-board co-design.

"For over a decade, Cadence has worked with the industry's largest semiconductor companies to design leading Ethernet SoCs for networking and high-performance computing applications, while also helping drive the development of Ethernet standards," said Vishal Kapoor, vice president, product marketing, SoC Realization at Cadence. "As large scale data centers begin their transition to 40/100 GbE over the next three years, we want to empower our customers with the tools they need to take advantage of the anticipated rapid growth in the ultra high-speed Gigabit Ethernet market."

The Dell'Oro Group forecasts robust growth in 40 Gigabit Ethernet and 100 Gigabit Ethernet with the market for these combined technologies expected to exceed $3B by 2016.

The Cadence 40/100 GbE MAC and PCS IP cores support the latest version of the IEEE 802.3ba-2010 Ethernet specification and sub-specifications including Energy Efficient Ethernet for power savings during idle time. The IP includes a host of configurable features such as Ethernet address match logic and frame- and priority-based flow control mechanisms for application-based customization of traffic control. In addition, a programmable inter-frame gap feature enables precise packet flow control to avoid equipment overload. Finally, the IP provides comprehensive monitoring features including error/status word for each frame that is transmitted and received; remote monitoring (RMON) and management information base (MIB) support. The 40/100 GbE MAC IP supports Gigabit media independent interfaces (XLGMII and CGMII) for connection to the attached PHY layer device, whereas the 40/100 GbE PCS IP supports integration with four/ten 10 Gigabit SerDes.

Availability
The design IP, including MAC and PCS, as well VIP, emulation and virtual prototyping support, are available immediately.