SAN JOSE, Calif. - Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced that Airoha Technology Corp. adopted the Cadence Encounter RTL Compiler and Cadence Encounter Test solutions after a rigorous competitive evaluation, and achieved a 15 percent reduction in power consumption and 10 percent reduction in test pattern count on a Bluetooth wireless radio chip. Encounter RTL Compiler employs unique global mapping technology and advanced clock gating to reduce power consumption without compromising design performance goals.
Airoha also deployed the Cadence Encounter Conformal Equivalence Checker and the Cadence Encounter Digital Implementation System on this chip. The full integration of Encounter RTL Compiler, Encounter Test and Conformal Equivalence Checker allowed Airoha to easily migrate from their existing flow to a more holistic front-end logic design environment.
"Cadence offers a well integrated solution, and takes almost no efforts to migrate. We were able to transfer an entire third-party synthesis flow over to Encounter RTL Compiler within just one day, saving time and allowing uninterrupted production for the engineering team," said Dr. David Chang, president and CEO of Airoha. "With this Cadence solution, we were able to provide the highest quality of silicon, faster time to market and more low power than would have been possible with our previous flow."
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available here .
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