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Cadence Design : Launches Xcelium Parallel Simulator, the Industry’s First Production-Proven Parallel Simulator

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02/27/2017 | 05:07pm CET


  • Delivers third generation of simulation with multi-core parallel computing as part of the industry-leading Cadence Verification Suite
  • Provides an average 2X improved single-core performance
  • Offers an average multi-core performance speed-up of 3X for RTL design simulation, 5X for gate-level simulation and 10X for DFT simulations running on today's servers

Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced the Xcelium Parallel Simulator, the industry's first production-ready third generation simulator. It is based on innovative multi-core parallel computing technology, enabling systems-on-chip (SoCs) to get to market faster. On average, customers can achieve 2X improved single-core performance and more than 5X improved multi-core performance versus previous generation Cadence simulators. The Cadence Xcelium simulator is production proven, having been deployed to early adopters across mobile, graphics, server, consumer, internet of things (IoT) and automotive projects. For more information on the Xcelium simulator, please visit www.cadence.com/go/xcelium.

'The ability for ARM and our partners to deliver products to customers' expectations is inexorably bound to rapid and rigorous verification,' said Hobson Bullman, general manager, Technology Services Group at ARM. 'The Xcelium Parallel Simulator has demonstrated a 4X speed-up for gate-level simulation and 5X for RTL simulation on ARM-based SoC designs. Based on these results, we expect Xcelium can enhance our ability to deliver the most complex SoCs in a fast and highly reliable way.'

'Fast, scalable simulation is key for us to meet the tight development schedules of our complex 28nm FD-SOI SoCs and ASICs for smart driving and industrial IoT,' said Francois Oswald, CPU team manager at STMicroelectronics. 'We measured 8X faster serial-mode DFT performance with the Cadence Xcelium Parallel Simulator, and therefore selected it as the standard simulation solution for our digital and mixed-signal SoC verification teams.'

The Xcelium simulator offers the following benefits aimed at accelerating system development:

  • Multi-core simulation improves runtime while also reducing project schedules: The third generation Xcelium simulator is built on the technology acquired from Rocketick and is the only fully-released simulator based on production-proven parallel simulation technology. It speeds runtime by an average of 3X for register-transfer level (RTL) design simulation, 5X for gate-level simulation and 10X for parallel design for test (DFT) simulation, potentially saving weeks to months on project schedules.
  • Broad applicability: The Xcelium simulator supports modern design styles and IEEE standards, enabling engineers to realize performance gains without recoding.
  • Easy to use: The Xcelium simulator's compilation and elaboration flow assigns the design and verification testbench code to the ideal engines and automatically selects the optimal number of cores for fast execution speed.
  • Incorporates several new patent-pending technologies to improve productivity: New features that speed overall SoC verification time include SystemVerilog testbench coverage for faster verification closure and parallel multi-core build.

'Verification is often the primary cost and schedule challenge associated with getting new, high-quality products to market,' said Dr. Anirudh Devgan, senior vice president and general manager of the Digital & Signoff Group and the System & Verification Group at Cadence. 'The Xcelium simulator combined with JasperGoldApps, the Palladium Z1 Enterprise Emulation Platform and the Protium S1 FPGA-Based Prototyping Platform offer customers the strongest verification suite on the market, enabling engineers to accelerate the pace of innovation.'

The new Xcelium simulator further extends the innovation within the Cadence Verification Suite and supports the company's System Design Enablement (SDE) strategy, which enables system and semiconductor companies to create complete, differentiated end products more efficiently. The Verification Suite is comprised of best-in-class core engines, verification fabric technologies and solutions that increase design quality and throughput, fulfilling verification requirements for a wide variety of applications and vertical segments.

In related news, Cadence also announced the delivery of another Verification Suite engine today, the Protium S1 FPGA-Based Prototyping Platform, which reduces prototyping time by up to 50 percent. For more information on the Protium platform, please visit www.cadence.com/go/protium-s1.

Cadence Design Systems Inc. published this content on 27 February 2017 and is solely responsible for the information contained herein.
Distributed by Public, unedited and unaltered, on 27 February 2017 16:07:13 UTC.

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Financials ($)
Sales 2017 1 930 M
EBIT 2017 475 M
Net income 2017 262 M
Finance 2017 37,4 M
Yield 2017 -
P/E ratio 2017 33,81
P/E ratio 2018 30,41
EV / Sales 2017 4,50x
EV / Sales 2018 4,17x
Capitalization 8 723 M
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Mean consensus OUTPERFORM
Number of Analysts 9
Average target price 29,7 $
Spread / Average Target -5,2%
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Lip-Bu Tan President, Chief Executive Officer & Director
John B. Shoven Chairman
Geoffrey G. Ribar Chief Financial Officer & Senior Vice President
Neil Kole Chief Information Officer & SVP
Roger S. Siboni Independent Director
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