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Cadence Design : Custom/Analog and Full-Flow Digital and Signoff Tools Enabled for GLOBALFOUNDRIES 7LP Process Node

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06/20/2017 | 03:01pm CEST

AUSTIN, Texas, June 20, 2017 /PRNewswire/ -- DESIGN AUTOMATION CONFERENCE -- Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that its custom/analog and full-flow digital and signoff tools are now enabled for v0.5 of the GLOBALFOUNDRIES 7nm Leading-Performance (7LP) FinFET semiconductor technology. The 7LP process node is expected to deliver 40 percent better performance and twice the area scaling than the previous 14nm FinFET technology.

GF has enabled the Cadence(®) implementation tools and reference flow for the 7LP platform, providing high-volume customers with the ability to create reliable, advanced-node chips for the high-performance compute (HPC), server/datacenter, premium mobility AP, machine learning and vision processing markets. To learn more about the Cadence full-flow digital and signoff solutions in the flow, visit www.cadence.com/go/gf7lpdands. For information about the Cadence custom/analog solutions in the flow, visit www.cadence.com/go/gf7lpcanda.

Cadence collaborated with GF on the development of the 7LP Process Design Kit (PDK), which is available for early customer designs. The tools in the flow include:

    --  Innovus((TM)) Implementation System: An advanced physical implementation
        tool, incorporating a massively parallel architecture that helps
        designers deliver high-quality SoCs in less time with best-in-class PPA
    --  Genus((TM)) Synthesis Solution: An RTL synthesis and physical synthesis
        engine that improves productivity challenges faced by RTL designers,
        delivering up to 5X faster synthesis turnaround times
    --  Tempus((TM)) Timing Signoff Solution: A complete timing analysis tool
        that improves signoff timing closure via massively parallel processing
        and physically aware timing optimization
    --  Quantus((TM)) QRC Extraction Solution: A parasitic extraction tool that
        provides faster runtimes for single- and multi-corner extraction and
        best-in-class accuracy versus foundry golden
    --  Voltus((TM)) IC Power Integrity Solution: A cell-level power integrity
        solution supports comprehensive electromigration and IR drop (EM/IR)
        design rules and requirements while providing full-chip SoC power
        signoff accuracy
    --  Voltus-Fi Custom Power Integrity Solution: A transistor-level power
        integrity solution supports comprehensive EM/IR design rules and
        requirements while providing SPICE-level power signoff accuracy for
        analog, memory and custom digital IP blocks
    --  Physical Verification System: Includes advanced technologies and rule
        decks to support design rule checks (DRCs), layout versus schematic
        (LVS), advanced metal fill, yield-scoring, voltage-dependent checks and
        in-design signoff
    --  Manufacturability and Variability Solutions (MVS): Delivers
        design-for-manufacturability (DFM) and variability analysis and
        optimization, including in-design detection and automated fixing
    --  Spectre(®) Classic Simulator, Spectre Accelerated Parallel Simulator
        (APS) and Spectre eXtensive Partitioning Simulator (XPS): These products
        deliver fast and accurate circuit simulation of complex analog, radio
        frequency (RF) and mixed-signal circuits with full support for
        advanced-node device models and parasitics
    --  Virtuoso(®) Analog Design Environment (ADE) Product Suite: Enables
        engineers to fully explore, analyze and verify designs, ensuring that
        variation is addressed and design quality is fully optimized within
        compressed design cycles
    --  Virtuoso Layout Suite: Supports custom/analog, digital, and mixed-signal
        designs at the device, cell, block, and chip levels, offering
        accelerated performance and productivity
    --  Virtuoso Schematic Editor: Provides numerous capabilities to facilitate
        fast and easy design entry, including design assistants that speed
        common tasks by as much as 5X
    --  Virtuoso Liberate((TM)) Characterization Solution: An ultra-fast
        standard cell, I/O, memory and complex multi-bit-cell library
        characterization solution that generates electrical cell views for
        timing, power and signal integrity, including advanced current source
        models (CCS and ECSM)

"High-volume semiconductor companies working to migrate to advanced-node designs can begin to use our 7LP process now," said Alain Mutricy, senior vice president of product management at GF. "We've collaborated with Cadence to ensure that its tools are supported at advanced nodes, enabling customers to create high-performance products for servers and datacenters, 5G connectivity, vision processing, and automotive."

"Cadence custom/analog, digital and signoff customers can engage with us now to start realizing the benefits of the GF 7LP process node and achieve power, performance and area goals," said Dr. Anirudh Devgan, executive vice president and general manager of the Digital & Signoff Group and System & Verification Group at Cadence. "Our work with GF demonstrates our joint commitment to enabling customers to create innovative SoCs that meet advanced technical requirements and aggressive time-to-market deadlines."

About Cadence

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence software, hardware and semiconductor IP are used by customers to deliver products to market faster. The company's System Design Enablement strategy helps customers develop differentiated products--from chips to boards to systems--in mobile, consumer, cloud datacenter, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For. Learn more at cadence.com.

© 2017 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.

For more information, please contact:
Cadence Newsroom
[email protected]

To view the original version on PR Newswire, visit:http://www.prnewswire.com/news-releases/cadence-customanalog-and-full-flow-digital-and-signoff-tools-enabled-for-globalfoundries-7lp-process-node-300476439.html

SOURCE Cadence Design Systems, Inc.

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Financials ($)
Sales 2017 1 932 M
EBIT 2017 480 M
Net income 2017 267 M
Finance 2017 34,1 M
Yield 2017 -
P/E ratio 2017 34,79
P/E ratio 2018 32,17
EV / Sales 2017 4,86x
EV / Sales 2018 4,49x
Capitalization 9 420 M
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Cadence Design Systems Inc Technical Analysis Chart | CDNS | US1273871087 | 4-Traders
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Mean consensus HOLD
Number of Analysts 9
Average target price 33,7 $
Spread / Average Target 0,07%
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Lip-Bu Tan President, Chief Executive Officer & Director
John B. Shoven Chairman
Geoffrey G. Ribar Chief Financial Officer & Senior Vice President
Neil Kole Chief Information Officer & Senior Vice President
Roger S. Siboni Independent Director
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