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Cadence Design Systems : Patent Issued for Layout Fixing Guideline System for Double Patterning Odd Cycle Violations

07/17/2014 | 12:24am US/Eastern

By a News Reporter-Staff News Editor at Journal of Engineering -- From Alexandria, Virginia, VerticalNews journalists report that a patent by the inventor Wang, Xiaojun (Cary, NC), filed on December 21, 2012, was published online on July 8, 2014.

The patent's assignee for patent number 8775983 is Cadence Design Systems, Inc. (San Jose, CA).

News editors obtained the following quote from the background information supplied by the inventors: "An integrated circuit ('IC') is a device (e.g., a semiconductor device) or electronic system that includes many electronic components, such as transistors, resistors, diodes, etc. These components are often interconnected to form multiple circuit components, such as gates, cells, memory units, arithmetic units, controllers, decoders, etc. An IC includes multiple layers of wiring that interconnect the IC's electronic and circuit components.

"Design engineers design ICs by transforming logical or circuit descriptions of the ICs' components into geometric descriptions, called design layouts. Design layouts typically include (1) circuit modules (i.e., geometric representations of electronic or circuit IC components) with pins and (2) interconnect lines (i.e., geometric representations of wiring) that connect the pins of the circuit modules. In this fashion, design layouts often describe the behavioral, architectural, functional, and structural attributes of the IC. To create design layouts, design engineers typically use electronic design automation ('EDA') applications. These applications provide sets of computer-based tools for creating, editing, analyzing, and verifying design layouts. The applications also render the layouts on a display device or to storage for displaying later.

"Fabrication foundries ('fabs') manufacture ICs based on the design layouts using a photolithographic process. Photolithography is an optical printing and fabrication process by which patterns on a photolithographic mask (i.e., 'photomask,' or 'mask') are imaged and defined onto a photosensitive layer coating a substrate. To fabricate an IC, photomasks are created using the IC design layout as a template. The photomasks contain the various geometries or shapes (i.e., features) of the IC design layout. The various geometries or shapes contained on the photomasks correspond to the various base physical IC elements that comprise functional circuit components such as transistors, interconnect wiring, vertical interconnect access (via) pads, as well as other elements that are not functional circuit elements but are used to facilitate, enhance, or track various manufacturing processes. Through sequential use of the various photomasks corresponding to a given IC in an IC fabrication process, a large number of material layers of various shapes and thicknesses with various conductive and insulating properties may be built up to form the overall IC and the circuits within the IC design layout.

"As more circuit features are packed into an IC design layout (e.g., manufacturing processes at feature sizes of 22 nm and below), the resolution of the photolithographic process makes it extremely difficult to fabricate the geometries or shapes on a single lithography mask. The difficulty stems from constraining factors in traditional photolithographic processes that limit the effectiveness of current photolithographic processes. Some such constraining factors are the lights/optics used within the photolithographic processing systems. Specifically, the lights/optics are band limited due to physical limitations (e.g., wavelength and aperture) of the photolithographic process. Therefore, the photolithographic process cannot print beyond a certain minimum width of a feature, minimum spacing between features, and other such physical manufacturing constraints.

"For a particular layer of the IC fabrication process, the pitch specifies the sum of the width of a feature and the space on one side of the feature separating that feature from a neighboring feature on the same layer. The minimum pitch for a layer is the sum of the minimum feature width and the minimum spacing between features on the same layer. Depending on the photolithographic process at issue, factors such as optics and wavelengths of light or radiation restrict how small the pitch may be made before features can no longer be reliably printed to a wafer or mask. As such, the smallest size of any features that can be created on a layer of an IC is limited by the minimum pitch for the layer.

"FIG. 1 illustrates a typical pitch constraint of a photolithographic process. In FIG. 1, a pitch 110 acts to constrain the spacing between printable features 120 and 130 of a design layout. While other photolithographic process factors such as the threshold 140 can be used to narrow the width 150 of the features 120 and 130, such adjustments do not result in increased feature density without adjustments to the pitch 110. As a result, increasing feature densities beyond a certain threshold is infeasible via a pitch constrained single exposure process.

"To enhance the feature density, the shapes on a single layer can be manufactured on two different photolithographic masks. This approach is often referred to as 'Double Patterning Lithography (DPL)' technology. FIG. 2 illustrates an example of this approach. In FIG. 2, a design layout 205 specifies three features 210-230 that are pitch constrained and therefore cannot be photolithographically printed with a conventional single exposure process. Analysis of the characteristics (e.g., the band limitation) of the available photolithographic process and of the design layout 205 results in the decomposition of the design layout 205 into a first exposure 240 for printing features 210 and 230 and a second exposure 250 for printing feature 220. As such, the features 210 and 230 are assigned to a first photomask for printing during the first exposure 240 and feature 220 is assigned to a second photomask for printing during the second exposure 250.

"FIG. 3 illustrates sending five shapes 301-305 of a design layout 300 to two different masks. The shape pairs of the shapes 301 and 302; the shapes 302 and 303; the shapes 303 and 304; and the shapes 303 and 305 are all pitch constrained. Therefore, the two shapes of each pair must be sent to two different masks 310 and 315. Accordingly, the shapes 301 and 303 are sent to a first mask 310. That is, the shapes 301 and 303 are printed during a first exposure in order to produce contours 320. Similarly, the shapes 302, 304, and 305 are sent to a second mask 315. That is, the shapes 302, 304, and 305 are printed during a second exposure in order to produce contours 325. The resulting union of the contours 320 and 325 generates pattern 330 that is sufficient to approximately reproduce the original design layout 300.

"When a gap exists between two shapes, meaning the two shapes are within the minimum same color spacing, the two shapes are considered connected. When shapes connect to form a loop and there are an odd number of shapes in the loop, it is not possible to assign colors in a way that all of the shapes are on a different mask from its neighbors. This error-causing loop will be referred to as an odd loop in this patent application.

"FIG. 4 illustrates an example printing error that is materialized on the physical wafer when three shapes 1-3 in an odd loop are sent to two different masks. As shown, the shapes 1-3 are divided into two sets of shapes 410 and 415, where the shape 2 is sent to the first of the two masks and the shapes 1 and 3 are sent to the second mask.

"Each set of shapes is printed during an exposure of a double exposure photolithographic printing process (e.g., a DPL process). That is, the set of shapes 410 (i.e., the shape 2) is printed during the first exposure in order to produce contours 420 and the set of shapes 415 is printed during the second exposure in order to produce contours 425.

"However, because the shape 1 and the shape 3 were too close (e.g., within the minimum same color spacing 710) in the pattern 405, the contour for the shape 1 and the contour for the shape 2 intersect in this example, resulting in a short. The resulting union of the contours 420 and 425 generates the pattern 430. As shown, the pattern 430 did not meet the specifications within the original design layout represented by the pattern 405 in which shapes 1 and 3 are not meant to connect to each other.

"Using DPL techniques creates a new challenge for the layout designers because the designers have to satisfy the requirements of DPL techniques in addition to Design Rule Checking (DRC) and Design For Manufacturability (DFM) requirements. Moreover, fixing a double patterning (DP) loop violation (an odd loop) is much more complex than fixing a DRC violation. This is because a DRC violation is usually a violation caused by a single shape or interaction of a few shapes whereas a DP loop violation is a set of spacing constraint violations between three or more shapes. It is also relatively more difficult to figure out whether moving a shape to fix a DP loop violation results in a new DP loop violation.

"There are several existing approaches that address DP loop violations. One of the approaches is editing layouts manually. This approach is time and manpower intensive because the designers have to go through several iterations of edits to figure out the problems and fix them. Thus, this approach has to rely on skills of the designers in finding a solution to a DP loop violation, which is not as straightforward as finding a solution for a DRC violation.

"Another of the existing approaches is an automatic Rip and Reroute technique. The Rip and Reroute technique rips the shapes and reroutes the shapes to resolve a design rule violation. The Rip and Reroute technique uses a minimum same color spacing as a spacing constraint. That is, this technique separates the shapes in a design layout such that all shapes are apart from one another at a distance greater than or equal to a minimum same color spacing. Using this technique therefore results in separating two shapes that have different colors at a distance that is greater than a distance at which shapes with different colors should be apart from each other.

"Some Rip and Reroute techniques may be track-based. When the technique is track-based, the technique assigns different colors to predefined tracks. Thus, track-based Rip and Reroute technique may not fully utilize all available space in the design layout because the shapes may not occupy all available track spaces. In addition, the Rip and Reroute technique is computation-intensive and slow because the shapes have to be ripped and rerouted. Also, this technique is of limited use for full custom layouts because the technique modifies existing routing topology to fix a design violation. Finally, the technique also requires connectivity information in the layout."

As a supplement to the background information on this patent, VerticalNews correspondents also obtained the inventor's summary information for this patent: "Some embodiments of the invention provide a method for automatically identifying and displaying double patterning loop violations (odd loops) in an IC design layout. The method of some embodiments also generates layout fixing guidelines (hints) for the resolution of the odd loops, identifying the hints by evaluating the effectiveness and feasibility of different potential resolutions and ensuring that hints do not create additional odd loops. The method of some embodiments also prioritizes or scores the resolution hints to facilitate efficient troubleshooting of odd loop violations and displays indications of the odd loops and the hints which a user can use to troubleshoot an odd loop violation.

"In some embodiments, the method first identifies one or more shape sets in the design layout. A shape set is a set of shapes in which one shape is within a threshold distance from at least one other shape. The method of some embodiments uses a graph in which the shapes are nodes or represented as the nodes. The method connects a pair of nodes with a link (e.g., a line or an edge) in the graph when the pair of shapes represented by the pair of nodes are within the threshold distance. In a graph representing a disjoint set, a node is connected to any other node by one or more links and nodes. A node is directly connected to another node when these two nodes are connected by a link.

"In some embodiments, the method identifies the DP loop violations in a design layout and displays the odd loops and resolution hints for each identified odd loop violation. The method receives shapes from a layer of a design layout from the design layouts and identifies odd loops within the layout. The method of some embodiments identifies the location of the loop as well as the shapes making up the odd loop.

"In some embodiments, the method identifies the error gaps of the odd loop. Error gaps are all of the spaces between shapes that make up an odd loop. Each error gap will be less than the minimum same color spacing of a layout. However, not all error gaps are hints. Hints are identified when the removal of a particular error gap would result in the removal of an odd loop without the creation of a new odd loop. In some embodiments, fixing or removing an error gap involves growing the error gap until it meets the minimum same color spacing requirement. When the error gap meets the minimum same color spacing requirement, the shapes on both sides of the error gap can be printed on a single mask and no longer create a DP loop violation.

"In some embodiments, the method evaluates the edges of the shapes on either side of the hint error gap to determine both the movability and the effectiveness of the hint. The movability measures a distance by which an edge of a hint error gap can be moved within the constraints of the design. The effectiveness measures the number of loops that may be removed by the breakage of a particular error gap. The method of some embodiments may also generate move instructions which are instructions used by an application to provide indications of a distance by which an edge needs to be moved in order to fix or remove a hint error gap.

"In some embodiments, the method evaluates the properties of the hints to prioritize or score each hint. The method sorts hints based on different qualities of the hint that may allow for efficient or simple resolution. These hints may be sorted for a particular loop, providing recommended solutions for a particular odd loop. These hints may also be sorted for an entire layer of a design layout, providing recommended hints to resolve all of the odd loops with the fewest adjustments.

"The preceding Summary is intended to serve as a brief introduction to some embodiments of the invention. It is not meant to be an introduction or overview of all of the inventive subject matter disclosed in this document. The Detailed Description that follows and the Drawings that are referred to in the Detailed Description will further describe the embodiments described in the Summary as well as other embodiments. Accordingly, to understand all the embodiments described by this document, a full review of the Summary, Detailed Description and the Drawings is needed. Moreover, the claimed subject matters are not to be limited by the illustrative details in the Summary, Detailed Description and the Drawing, but rather are to be defined by the appended claims, because the claimed subject matters can be embodied in other specific forms without departing from the spirit of the subject matters."

For additional information on this patent, see: Wang, Xiaojun. Layout Fixing Guideline System for Double Patterning Odd Cycle Violations. U.S. Patent Number 8775983, filed December 21, 2012, and published online on July 8, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8775983.PN.&OS=PN/8775983RS=PN/8775983

Keywords for this news article include: Cadence Design Systems Inc.

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