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Cadence Design : Full-Flow Digital and Signoff and Verification Suite Optimized to Support Arm Cortex-A75 and Cortex-A55 CPUs and Arm Mali-G72 GPU

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08/07/2017 | 04:46pm CEST

SAN JOSE, Calif., Aug. 7, 2017 /PRNewswire/ -- Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that its full-flow digital and signoff tools and the Cadence(®) Verification Suite have been optimized to support Arm(®) Cortex(®)-A75 and Cortex-A55 CPUs, based on Arm DynamIQ(TM) technology, and the Arm Mali((TM))-G72 GPU, the latest offerings from Arm for premium mobile, machine learning, and consumer devices. To accelerate the adoption of Arm's latest processors, Cadence delivered new 7nm-ready Rapid Adoption Kits (RAKs) for the Cortex-A75 and the Cortex-A55 CPUs, which include the DynamIQ Shared Unit (DSU) that provides a shared level 3 cache between the CPUs, and a 7nm-ready RAK for the Mali-G72 GPU.

Customers are already using the complete digital and signoff flow and the Cadence Verification Suite to tape out complex systems-on-chip (SoCs) containing the latest Arm Cortex and Mali processors. To learn more about the Cadence full-flow digital and signoff solutions that support the Cortex-A75, Cortex-A55, and Mali-G72 processors, please visit www.cadence.com/go/dandsarmraks7nm. For more information on the Cadence Verification Suite that enables Arm-based designs using the Cortex-A75, Cortex-A55 and Mali-G72 processors, please visit www.cadence.com/go/vsuitearm7nm.

The Cadence RAKs accelerate physical implementation, signoff, and verification of 7nm designs, allowing designers to deliver mobile and consumer devices to market faster. With the delivery of the new RAKs, Cadence is also providing specialized technical support for Arm IP implementation based on the deep collaboration between Arm and Cadence over many years.

The Cadence digital and signoff tools have been configured to provide optimal power, performance and area (PPA) results using the RAKs, which include scripts, an example floorplan, and documentation for Arm's 7nm IP libraries. The comprehensive Cadence RTL-to-GDS flow incorporates the following digital and signoff tools in the RAKs:

    --  Innovus((TM)) Implementation System: Statistical on-chip variation
        (SOCV) propagation and optimization results in improved timing, power,
        and area closure for 7nm designs
    --  Genus((TM)) Synthesis Solution: Register-transfer level (RTL) synthesis
        supports all the latest 7nm advanced-node requirements and provides
        convergent design closure using the Innovus Implementation System
    --  Conformal(®) Logic Equivalence Checking (LEC): Ensures the accuracy of
        logic changes and engineering change orders (ECOs) during the
        implementation flow
    --  Conformal Low Power: Enables the creation and validation of power intent
        in context of the design, combining low-power equivalence checking with
        structural and functional checks to allow full-chip verification of
        power-efficient designs
    --  Tempus((TM)) Timing Signoff Solution: Offers path-based,
        signoff-accurate and physically aware design optimization, providing the
        quickest path to tapeout
    --  Voltus((TM)) IC Power Integrity Solution: Static and dynamic analysis
        used during implementation and signoff ensures optimal power
    --  Quantus((TM)) QRC Extraction Solution: Fulfills all 7nm advanced-node
        requirements to ensure accurate correlation to final silicon

"The Cortex-A75 and Cortex-A55 CPUs deliver distributed intelligence from edge-to-cloud, and pairing them with the Mali-G72 GPU enables consumers to experience stunning graphics efficiently across multiple devices," said Nandan Nayampally, vice president and general manager, Compute Products Group, Arm. "By continuing to collaborate with Cadence on the delivery of new digital implementation and signoff RAKs along with optimization of the Cadence Verification Suite, our mutual customers can quickly integrate and augment their differentiated solutions for next-generation devices."

The Cadence Verification Suite that has also been optimized for Arm-based designs includes:

    --  JasperGold(®) Formal Verification Platform: Enables IP and subsystem
        verification including formal proofs for Arm AMBA(®) protocols
    --  Xcelium(®) Parallel Logic Simulation: Provides production-proven
        multi-core simulation accelerating SoC development and validation of
        Arm-based designs
    --  Palladium(®) Z1 Enterprise Emulation Platform: Includes hybrid
        technology that is integrated with Arm Fast Models for up to 50X faster
        OS and software bring-up and up to 10X faster software-based testing in
        addition to Dynamic Power Analysis technology for low power
    --  Protium((TM)) S1 FPGA-Based Prototyping Platform: Integration with the
        Palladium Z1 enterprise emulation platform combined with Arm DS-5
        provides pre-silicon embedded software debug
    --  vManager((TM)) Planning and Metrics: Metric-driven verification across
        the JasperGold platform, Xcelium simulation, Palladium Z1 platform and
        Cadence VIP solutions for Arm-based SoC verification convergence
    --  Perspec((TM)) System Verifier: Provides software-driven use-case
        verification with the PSLib for Armv8 architectures, delivering up to
        10X productivity improvement versus typical manual test development
    --  Indago((TM)) Debug Platform: RTL design, testbench and embedded software
        debug capabilities synchronized with Arm CPUs for accurate combined
        views of hardware and software
    --  Cadence Verification Workbench: Integrates with Arm Socrates((TM))
        packaged Armv8 IP and VIP for fast SoC integration and UVM testbench
    --  Cadence Interconnect Workbench: Provides fast performance analysis and
        verification of Arm CoreLink((TM)) interconnect intellectual property
        (IP)-based systems in combination with Xcelium simulation, the Palladium
        Z1 platform, and Cadence Verification IP
    --  Verification IP Portfolio: Enables IP and SoC verification including Arm
        AMBA interconnect, supporting Xcelium simulation, the JasperGold
        platform, and the Palladium Z1 platform

"We worked closely with Arm to optimize our advanced digital implementation and signoff solutions and our verification solutions for the new Arm CPUs and GPU so our customers can efficiently create 7nm mobile and consumer designs," said Dr. Anirudh Devgan, executive vice president and general manager of the Digital & Signoff Group and the System & Verification Group at Cadence. "Designers using the RAKs and the Cadence Verification Suite can benefit from improved PPA and reduced project times, while creating the most advanced Arm-based products."

About Cadence
Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence software, hardware and semiconductor IP are used by customers to deliver products to market faster. The company's System Design Enablement strategy helps customers develop differentiated products--from chips to boards to systems--in mobile, consumer, cloud datacenter, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For. Learn more at cadence.com.

© 2017 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners. AMBA, Arm, CoreLink, Cortex, DynamIQ, Mali and Socrates are trademarks or registered trademarks of Arm (or its subsidiaries) in the EU and/or elsewhere. All other trademarks are the property of their respective owners.

For more information, please contact:
Cadence Newsroom

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SOURCE Cadence Design Systems, Inc.

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Financials ($)
Sales 2017 1 935 M
EBIT 2017 504 M
Net income 2017 271 M
Finance 2017 24,5 M
Yield 2017 -
P/E ratio 2017 37,43
P/E ratio 2018 36,03
EV / Sales 2017 5,38x
EV / Sales 2018 4,97x
Capitalization 10 429 M
Duration : Period :
Cadence Design Systems Inc Technical Analysis Chart | CDNS | US1273871087 | 4-Traders
Technical analysis trends CADENCE DESIGN SYSTEMS INC
Short TermMid-TermLong Term
Income Statement Evolution
Mean consensus HOLD
Number of Analysts 9
Average target price 36,5 $
Spread / Average Target -1,9%
EPS Revisions
Lip-Bu Tan President, Chief Executive Officer & Director
John B. Shoven Chairman
Geoffrey G. Ribar Chief Financial Officer & Senior Vice President
Neil Kole Chief Information Officer & Senior Vice President
Roger S. Siboni Independent Director
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