By a News Reporter-Staff News Editor at Journal of Engineering -- Maxim Integrated Products, Inc. (San Jose, CA) has been issued patent number 9105750, according to news reporting originating out of Alexandria, Virginia, by VerticalNews editors.
The patent's inventors are Samoilov, Arkadii V. (Saratoga, CA); Parent, Tyler (Beaverton, OR); Ying, Xuejun (San Jose, CA).
This patent was filed on June 2, 2014 and was published online on August 11, 2015.
From the background information supplied by the inventors, news correspondents obtained the following quote: "Consumer electronic devices, in particular, mobile electronic devices such as smart phones, tablet computers, and so forth, increasingly employ smaller, more compact components to furnish their users with desired features. Such devices often employ three dimensional integrated circuit devices (3D IC). Three-dimensional integrated circuit devices are semiconductor devices that employ two or more layers of active electronic components. Through-substrate vias (TSV) interconnect electronic components on the different layers (e.g., different substrates) of the device allowing the devices to be integrated vertically as well as horizontally. Consequently, three-dimensional integrated circuit devices can provide increased functionality within a smaller, more compact footprint than do conventional two-dimensional integrated circuit devices."
Supplementing the background information on this patent, VerticalNews reporters also obtained the inventors' summary information for this patent: "Semiconductor devices are described that include two or more substrates bonded together. Through-substrate vias (TSV) furnish electrical interconnectivity to electronic components formed in the substrates. In implementations, the semiconductor devices are fabricated by bonding two or more semiconductor wafers together using a patterned adhesive material such as a patterned dielectric. The patterned adhesive material allows for lateral expansion of the adhesive material when the wafers are pressed together during the bonding process. For example, a top wafer may be bonded to a bottom wafer by applying adhesive material to a first (upper) surface of the bottom wafer. The adhesive material is then patterned. The patterned adhesive material may then be used to bond the first (lower) surface of the top wafer to the first (upper) surface of the bottom wafer. Vias may then be formed through the top wafer and the patterned adhesive material to furnish electrical interconnection between the wafers. This process may be repeated to bond additional wafers to the second (upper) surface of the top wafer. The bonded wafers may then be segmented into individual semiconductor devices.
"This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter."
For the URL and additional information on this patent, see: Samoilov, Arkadii V.; Parent, Tyler; Ying, Xuejun. Semiconductor Device Having a Through-Substrate via. U.S. Patent Number 9105750, filed June 2, 2014, and published online on August 11, 2015. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=9105750.PN.&OS=PN/9105750RS=PN/9105750
Keywords for this news article include: Technology Companies, Electronic Components, Semiconductor - Broad Line Companies.
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