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Raytheon : Patent Issued for Use of an External Getter to Reduce Package Pressure (USPTO 9570321)

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02/24/2017 | 11:25am CET

By a News Reporter-Staff News Editor at Journal of Engineering -- From Alexandria, Virginia, VerticalNews journalists report that a patent by the inventors Black, Stephen H. (Tennessee Ridge, TN); Kennedy, Adam M. (Santa Barbara, CA), filed on October 20, 2015, was published online on February 14, 2017.

The patent's assignee for patent number 9570321 is RAYTHEON COMPANY (Waltham, MA).

News editors obtained the following quote from the background information supplied by the inventors: "A conventional wafer level package (WLP) includes a device wafer having one or more devices disposed on a substrate that is bonded to a cap or lid wafer using bonding structures. The finished WLP forms a hermetically sealed interior to protect the devices and extend their useful life. Getters have historically been used to reduce the pressure within the sealed vacuum cavity of WLP, and to maintain the vacuum over the life of the device. A getter is typically a material that, when activated, captures gas molecules in a vacuum or low pressure environment. The getter absorbs, adsorbs, and/or physically entraps oxygen and other molecules and impurities that are outgassed from the components packaged within the WLP, and in certain instances, may also trap impurities that leak through the WLP from the external environment. The getter is typically made from materials that react with the impurities to form stable compounds, such as oxides, carbides, hydrides, and nitrides.

"As die sizes shrink, the amount of space that can be allocated to the getter within the WLP is also reduced. During the wafer bonding process, there is thus an increased potential to contaminate these small getters. There is therefore a need for a method or system that can compensate for this loss in getter size and subsequent increase in the risk of contamination."

As a supplement to the background information on this patent, VerticalNews correspondents also obtained the inventors' summary information for this patent: "Aspects and embodiments are directed to devices and methods that provide a layer of getter material disposed on at least a portion of an external region of one or both of the wafers comprising a WLP.

"According to one embodiment, a wafer for use in forming a wafer level package comprises a substrate having a surface defined by a wafer level package (WLP) region and an external region, and a layer of getter material disposed on at least a portion of the external region of the surface of the substrate.

"In one example, the external region comprises a saw-to-reveal (STR) region. In on example, the STR region is defined by a two-dimensional pattern of intersecting horizontal and vertical saw lanes, and the layer of getter material is disposed on at least a portion of at least one of the horizontal and vertical saw lanes. According to a further example, the layer of getter material is disposed on at least a portion of both the horizontal and the vertical saw lanes. According to another example, the STR region is defined by a series of parallel saw lanes. According to one example, the layer of getter material is continuous.

"In one example, the substrate is a window cap wafer and at least a portion of the WLP region includes an optically transmissive window material. In another example, the substrate is a device wafer and at least a portion of the WLP region includes at least one semiconductor device. In one example, the layer of getter material is further disposed on at least a portion of the WLP region.

"In one example, the getter material comprises at least one of titanium (Ti), zirconium (Zr), ruthenium (Ru), tantalum (Ta), hafnium (Hf), lanthanum (La) and molybdenum (Mo). In one example, the thickness of the layer of getter material is in a range of about 1000 Angstroms to about 10,000 Angstroms.

"According to another embodiment, a method for forming a wafer comprises providing a substrate, masking a surface of the substrate with a masking material to at least partially define an external region, wherein at least a portion of the external region is open to the surface of the substrate, and depositing a layer of getter material on the surface of the substrate through the open portion of the external region.

"In one example, masking the surface with the masking material at least partially defines a WLP region, wherein at least a portion of the WLP region is open to the surface of the substrate, and the layer of getter material is further deposited on the surface of the substrate through the open portion of the WLP region. In one example, the external region comprises an STR region defined by at least one saw lane. In a further example, depositing forms a continuous layer of getter material.

"According to another embodiment, a method for forming a wafer level package comprises providing a window cap wafer and a device wafer, each of the window cap wafer and the device wafer having a surface defined by a WLP region and an external region, wherein a layer of getter material is disposed on at least a portion of the external region of at least one of the window cap wafer and the device wafer, aligning the window cap wafer with the device wafer, and bonding the window cap wafer and the device wafer to each other to form the wafer level package.

"In one example, during the bonding at least a portion of one or more impurities present on at least one of the window cap wafer and the device wafer outgas into the layer of getter material. In another example, the layer of getter material reduces pressure in a region between the window cap wafer and the device wafer during the bonding.

"In one example the bonding is performed under vacuum and comprises heating the layer of getter material to a temperature such that it is activated during bonding. In a further example, the layer of getter material is heated to a temperature of at least 300.degree. C.

"According to another embodiment, a wafer for use in a level package comprises a substrate having a surface defined by a WLP region and an external region, the external region including a plurality of intersecting horizontal and vertical saw lanes, and at least one layer of getter material disposed on at least a portion of each of the WLP region and the external regions of the surface of the substrate.

"Still other aspects, embodiments, and advantages of these example aspects and embodiments, are discussed in detail below. Moreover, it is to be understood that both the foregoing information and the following detailed description are merely illustrative examples of various aspects and embodiments, and are intended to provide an overview or framework for understanding the nature and character of the claimed aspects and embodiments. Embodiments disclosed herein may be combined with other embodiments, and references to 'an embodiment,' 'an example,' 'some embodiments,' 'some examples,' 'an alternate embodiment,' 'various embodiments,' 'one embodiment,' 'at least one embodiment,' 'this and other embodiments,' 'certain embodiments,' or the like are not necessarily mutually exclusive and are intended to indicate that a particular feature, structure, or characteristic described may be included in at least one embodiment. The appearances of such terms herein are not necessarily all referring to the same embodiment."

For additional information on this patent, see: Black, Stephen H.; Kennedy, Adam M.. Use of an External Getter to Reduce Package Pressure. U.S. Patent Number 9570321, filed October 20, 2015, and published online on February 14, 2017. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=9570321.PN.&OS=PN/9570321RS=PN/9570321

Keywords for this news article include: RAYTHEON COMPANY, Risk and Prevention.

Our reports deliver fact-based news of research and discoveries from around the world. Copyright 2017, NewsRx LLC

(c) 2017 NewsRx LLC, source Science Newsletters

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EBIT 2017 3 220 M
Net income 2017 2 168 M
Debt 2017 1 755 M
Yield 2017 2,03%
P/E ratio 2017 20,61
P/E ratio 2018 18,32
EV / Sales 2017 1,86x
EV / Sales 2018 1,77x
Capitalization 44 896 M
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