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Sony : Patent Issued for Semiconductor Device with Less Positional Deviation between Aperture and Solder (USPTO 10014248)

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07/12/2018 | 07:55pm CEST

By a News Reporter-Staff News Editor at Electronics Newsweekly -- A patent by the inventors Murai, Makoto (Tokyo, JP); Takaoka, Yuji (Kanagawa, JP); Yamada, Hiroyuki (Kanagawa, JP); Sato, Kazuki (Kanagawa, JP); Imai, Makoto (Tokyo, JP), filed on June 5, 2015, was published online on July 3, 2018, according to news reporting originating from Alexandria, Virginia, by VerticalNews correspondents.

Patent number 10014248 is assigned to Sony Corporation (Tokyo, JP).

The following quote was obtained by the news editors from the background information supplied by the inventors: "In recent years, apparatuses having picture output functions, e.g., smartphones, tablet computers, television receivers, and game machines, have had remarkable improvement in display resolution. For adaptation thereto, there has been expansion of a memory band desired for an image processor LSI (Large Scale Integrated Circuit) installed in such apparatuses. Known techniques to achieve a wide memory band may include Chip on Chip (CoC), as disclosed in Patent Literature 1. But the CoC technique may tend to incur higher costs, because of use of DRAM (Dynamic Random Access Memory) having a special interface, or use of techniques such as fine connection using microbumps. A general approach may be, therefore, to use a plurality of DRAMs having a standard DDR (Double Data Rate) interface and to ensure the memory band by increasing the number of connection channels between the image processor LSI and the DRAMs. A 64-bit interface is in actual use in apparatuses such as smartphones, and the use of such an interface is expected to be spreading in the future.

"Moreover, miniaturization of semiconductor devices has allowed for integration of a greater number of transistors in a chip. This has made it possible to integrate even more functions in one chip. For example, an application processor currently used in the smartphone or the tablet computer, and the LSI incorporated in a digital television receiver mainly use what unitizes CPU (Central Processing Unit), GPU (Graphics Processing Unit), and various interfaces as one chip.

"Such advances in multi-channeling of a memory interface and in functional integration in one chip have caused a tendency of an increase in the number of terminals that connect the LSI to outside. In related arts, a packaging method has been generally adopted in which a semiconductor chip is connected to a packaging substrate by wire bonding. In recent years, however, in order to adapt to the increase in the connection terminals, adoption of a so-called flip chip technique has been increasing. The flip chip technique involves connecting the semiconductor chip to the packaging substrate with use of solder bumps. In particular, a technique generally used in the flip chip technique is called C4 (Controlled Collapse Chip Connection), as disclosed in, for example, Patent Literature 2.

"In the C4 technique, on side of the packaging substrate, a solder resist may be provided in advance with apertures. The apertures each may have a substantially same size as a size of a solder bump to be used for connection. A paste solder material may be printed in the apertures. Then, a chip provided in advance with solder bumps may be mounted on the printed solder material, with use of flux. By a batch reflow method, the solder may melt to form connection. An underfill resin may be filled for sealing, between the chip and the packaging substrate. With this technique used, miniaturization of an inter-terminal pitch may become difficult, for the following reasons. First, in order to ensure a gap between the chip and the packaging substrate to fill the underfill resin, it is desirable to increase a diameter of the solder bump formed on side of the chip. Second, the solder paste may be formed by a printing method, causing difficulty in formation of fine patterns. Accordingly, the pitch between the connection terminals may become about 150 .mu.m to 180 .mu.m both inclusive. This leads to expectation of difficulty in adaptation to an increase in the number of signals in the future, or to chip shrinkage due to device miniaturization.

"In view of the current situation as described above, Patent Literature 3 discloses a technique that involves performing flip chip directly on wirings, for purpose of a further increase in signal terminal density and reduction in substrate costs. In the existing C4 technique, a land having a larger size than the bump diameter may be formed on the packaging substrate. In contrast, in this technique, a bump may be pressed onto a wiring having a smaller width than a bump diameter, to join the bump and the wiring together, with the wiring forcing itself into the bump. Thus, this technique has made improvement in an effort to attain high bonding strength even in a case with use of bumps having small diameters. Also, a bump structure may be generally used in which solder plating is performed on a metal pillar, or a so-called pillar. This makes it possible to ensure the gap, between the chip and the packaging substrate, desirable for injection of the underfill resin even in the case with use of bumps having small diameters.

"A shortened pitch between the bumps may naturally result in possibility of occurrence of a short circuit between wirings. Patent Literature 4 therefore proposes to selectively cover a spot that is concerned about the occurrence of the short circuit with a masking material such as a solder resist. But this structure may cause the following disadvantages. First, the partially-formed masking material may easily peel off because of lack of continuity with other masking materials formed on the packaging substrate. When the partially-formed masking material peels off during an assembly process, there may be expectation of hindrance to injection of the underfill resin, or failure to prevent the short circuit. Second, the wirings are exposed in other than the spot where the masking material is partially formed. This causes possibility of the occurrence of the short circuit due to the solder material. Moreover, in a case with low adhesion between the underfill resin and the packaging substrate, a cavity may be formed between the wirings. In a case of moisture absorption, there may be concern about occurrence of migration. Third, because the masking material has an aperture in wide ranges, the wirings may easily peel off from an insulating layer of the packaging substrate, due to stress during the assembly process or after shipment of a product. This may cause lowered operation reliability.

"To cope with the disadvantages described above, Patent Literature 5 proposes a technique to selectively provide the masking material (solder resist) with an aperture at a connecting part between the wiring and the bump. Such a structure allows for lower probability of the occurrence of the short circuit between the adjacent wirings."

In addition to the background information obtained for this patent, VerticalNews journalists also obtained the inventors' summary information for this patent: "On the other hand, in the method described in Patent Literature 5, however, there is possibility of the following disadvantage. In heating for solder bonding during the assembly process, there may be deviation between a position of the aperture of the solder resist and a position of the solder, due to a difference in thermal expansion coefficients of the chip and the packaging substrate. As a result, the solder may run on the solder resist film, causing the short circuit with the adjacent wiring.

"It is to be noted that Patent Literature 6 discloses a technique in which paste solder may be formed in advance on the wiring side, and a stud bump may be pressed onto the paste solder, to form flip chip connection. The stud bump may be made of a material that allows the solder to be wet upward, e.g., gold. In this case, Patent Literature 6 discloses an improvement for suppression of the short circuit, in which the wiring on the packaging substrate may be provided in advance with a widened part, so as to allow the solder to be easily pooled at the widened part of the wiring. But this structure still allows the wirings to be exposed at a narrow pitch, and fails to provide sufficient countermeasures against the suppression of the short circuit.

"It is therefore desirable to provide a semiconductor device and a method of manufacturing the same that make it possible to alleviate influence of positional deviation between an aperture and a solder-including electrode, and to suppress a short circuit between adjacent wirings.

"A semiconductor device according to an embodiment of the disclosure includes a semiconductor chip, and a packaging substrate on which the semiconductor chip is mounted. The semiconductor chip includes a chip body and a plurality of solder-including electrodes provided on an element-formation surface of the chip body. The packaging substrate includes a substrate body, a plurality of wirings, and a solder resist layer, in which the plurality of wirings and the solder resist layer are provided on a front surface of the substrate body. The solder resist layer is provided as a continuous layer on the front surface of the substrate body and the plurality of wirings, and has an aperture on each of the plurality of wirings. The aperture has a planar shape elongated in a lengthwise direction of the wiring inside the aperture, with a length of the aperture adjusted in accordance with a thermal expansion coefficient of the packaging substrate.

"In the semiconductor device according to the embodiment of the disclosure, the aperture of the solder resist layer has the planar shape elongated in the lengthwise direction of the wiring inside the aperture. The length of the aperture is adjusted in accordance with the thermal expansion coefficient of the packaging substrate. Accordingly, in heating for solder bonding during an assembly process, there is little possibility that the solder runs on the solder resist layer even in a case with positional deviation between the aperture and the solder-including electrode due to a difference in thermal expansion coefficients of the semiconductor chip and the packaging substrate. Thus, influence of the positional deviation between the aperture and the solder-including electrode is alleviated, leading to suppression of a short circuit between adjacent wirings.

"A first method of manufacturing a semiconductor device according to an embodiment of the disclosure includes: aligning a semiconductor chip with a packaging substrate, in which the semiconductor chip includes a chip body and a plurality of solder-including electrodes provided on an element-formation surface of the chip body, and the packaging substrate includes a substrate body, a plurality of wirings, and a solder resist layer, in which the plurality of wirings and the solder resist layer are provided on a front surface of the substrate body; temporarily bonding the semiconductor chip to the packaging substrate; connecting the plurality of solder-including electrodes to the plurality of wirings, by reflow heating; and injecting an underfill resin between the semiconductor chip and the packaging substrate, and curing the underfill resin. The solder resist layer is provided as a continuous layer on the front surface of the substrate body and the plurality of wirings, and has an aperture on each of the plurality of wirings. The aperture has a planar shape elongated in a lengthwise direction of the wiring inside the aperture, with a length of the aperture adjusted in accordance with a thermal expansion coefficient of the packaging substrate.

"A second method of manufacturing a semiconductor device according to an embodiment of the disclosure includes: aligning a semiconductor chip with a packaging substrate, in which the semiconductor chip includes a chip body and a plurality of solder-including electrodes provided on an element-formation surface of the chip body, and the packaging substrate includes a substrate body, a plurality of wirings, and a solder resist layer, in which the plurality of wirings and the solder resist layer are provided on a front surface of the substrate body; connecting the plurality of solder-including electrodes to the plurality of wirings, by heating the semiconductor chip at a temperature equal to or higher than a melting point of the solder, and by pressure-bonding the semiconductor chip to the packaging substrate; and injecting an underfill resin between the semiconductor chip and the packaging substrate, and curing the underfill resin. The solder resist layer is provided as a continuous layer on the front surface of the substrate body and the plurality of wirings, and has an aperture on each of the plurality of wirings. The aperture has a planar shape elongated in a lengthwise direction of the wiring inside the aperture, with a length of the aperture adjusted in accordance with a thermal expansion coefficient of the packaging substrate.

"A third method of manufacturing a semiconductor device according to an embodiment of the disclosure includes: supplying an underfill resin on a packaging substrate, in which the packaging substrate includes a substrate body, a plurality of wirings, and a solder layer, in which the plurality of wirings and the solder resist layer are provided on a front surface of the substrate body; aligning a semiconductor chip with the packaging substrate, in which the semiconductor chip includes a chip body and a plurality of solder-including electrodes provided on an element-formation surface of the chip body; and connecting the plurality of solder-including electrodes to the plurality of wirings, while curing the underfill resin, by heating the semiconductor chip at a temperature equal to or higher than a melting point of the solder, and by pressure-bonding the semiconductor chip to the packaging substrate. The solder resist layer is provided as a continuous layer on the front surface of the substrate body and the plurality of wirings, and has an aperture on each of the plurality of wirings. The aperture has a planar shape elongated in a lengthwise direction of the wiring inside the aperture, with a length of the aperture adjusted in accordance with a thermal expansion coefficient of the packaging substrate.

"According to the semiconductor device of the embodiment of the disclosure, or the first to third methods of manufacturing the semiconductor devices of the embodiments of the disclosure, the aperture of the solder resist layer has the planar shape elongated in the lengthwise direction of the wiring inside the aperture. The length of the aperture is adjusted in accordance with the thermal expansion coefficient of the packaging substrate. Hence, it is possible to alleviate the influence of the positional deviation between the aperture and the solder-including electrode, leading to the suppression of the short circuit between the adjacent wirings.

"It is to be noted that some effects described here are not necessarily limitative, and any of other effects described herein may be achieved."

URL and more information on this patent, see: Murai, Makoto; Takaoka, Yuji; Yamada, Hiroyuki; Sato, Kazuki; Imai, Makoto. Semiconductor Device with Less Positional Deviation between Aperture and Solder. U.S. Patent Number 10014248, filed June 5, 2015, and published online on July 3, 2018. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=10014248.PN.&OS=PN/10014248RS=PN/10014248

Keywords for this news article include: Asia, Japan, Business, Semiconductor, Microtechnology, Sony Corporation, Health and Medicine, Electronics Companies, Electronic Equipment Companies.

Our reports deliver fact-based news of research and discoveries from around the world. Copyright 2018, NewsRx LLC

(c) 2018 NewsRx LLC, source Technology Newsletters

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