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STMICROELECTRONICS : Patent Issued for Layout and Pad Floor Plan of Power Transistor for Good Performance of SPU and STOG

04/17/2014 | 03:37am US/Eastern
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By a News Reporter-Staff News Editor at Journal of Engineering -- According to news reporting originating from Alexandria, Virginia, by VerticalNews journalists, a patent by the inventors Zhong, Guo Hua (Shenzhen, CN); Yang, Mei (Shenzhen, CN), filed on May 30, 2013, was published online on April 8, 2014.

The assignee for this patent, patent number 8691684, is STMicroelectronics (Shenzhen) R&D Co. Ltd. (Shenzhen, CN).

Reporters obtained the following quote from the background information supplied by the inventors: "The disclosure generally relates to the field of power transistors.

"Power circuits are generally susceptible to issues related to power dissipation, such as concentrated heat and current densities. Power dissipation, simply put, is the product of current flowing through a device that has some amount of resistance. The dissipation of power in a device over a period of time produces undesirable heat, which may, if in sufficient quantity, cause melting in portions of the device. Melting in semiconductor devices generally leads to operational failure.

"Current density is a measurement of electric current through an area and can also lead to device malfunction. For example, when the path for current to flow becomes restricted to an area that is relatively small for the amount of current flowing, the current density increases. A sufficient increase in current density begins to break down the material through which the current is flowing. This breakdown, similar to undesirable amounts of heat, generally leads to device failure."

In addition to obtaining background information on this patent, VerticalNews editors also obtained the inventors' summary information for this patent: "The following disclosure relates to a transistor with improved heat and current density disbursement. In one embodiment, metal layers associated with a source are interleaved with metal layers associated with a drain. The metal layers of this embodiment are interleaved with fingers of metal.

"In another embodiment, the metal fingers include a lower metal layer and an upper metal layer, and the upper metal layer is deposited directly on the lower metal layer without the use of a via or inter-metal connector.

"In one embodiment, pads for the source and drain are substantially parallel to one another so as to distribute the current density across a long edge of a source pad or a drain pad. Distributing the current density across a long edge of a source pad or a drain pad will increase the non-destructive current capacity of the transistor."

For more information, see this patent: Zhong, Guo Hua; Yang, Mei. Layout and Pad Floor Plan of Power Transistor for Good Performance of SPU and STOG. U.S. Patent Number 8691684, filed May 30, 2013, and published online on April 8, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=77&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=3839&f=G&l=50&co1=AND&d=PTXT&s1=20140408.PD.&OS=ISD/20140408&RS=ISD/20140408

Keywords for this news article include: STMicroelectronics.

Our reports deliver fact-based news of research and discoveries from around the world. Copyright 2014, NewsRx LLC

(c) 2014 Journal of Engineering via VerticalNews.com

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