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STMicroelectronics : Patent Issued for Negative Charge Pump with Soft Start (USPTO 9653990)

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05/25/2017 | 11:09pm CEST

By a News Reporter-Staff News Editor at Journal of Engineering -- STMicroelectronics (Shenzhen) R&D Co. Ltd (Shenzhen, CN) has been issued patent number 9653990, according to news reporting originating out of Alexandria, Virginia, by VerticalNews editors.

The patent's inventors are Wang, Meng (Shenzhen, CN); Zhou, Xue Lian (Shenzhen, CN).

This patent was filed on December 1, 2015 and was published online on May 16, 2017.

From the background information supplied by the inventors, news correspondents obtained the following quote: "Reference is made to FIG. 1 showing a circuit diagram of a conventional negative charge pump circuit 10. The circuit 10 includes a first CMOS switching circuit 12 and a second CMOS switching circuit 14. Each switching circuit 12 and 14 is formed by a series-connected pair of MOSFETs (drive transistors) including a p-channel transistor 16 and an n-channel transistor 18. The first CMOS switching circuit 12 is connected between a positive voltage supply node Vpos and a ground reference node Vgnd (with the source of transistor 16 connected to the positive voltage supply node Vpos and the source of transistor 18 connected to the ground reference node Vgnd). The second CMOS switching circuit 14 is connected between the ground reference node Vgnd and a negative voltage output node Vneg (with the source of transistor 16 connected to the ground reference node Vgnd and the source of transistor 18 connected to the negative voltage output node Vneg). The transistors 16 and 18 have their source-drain paths connected to each other at the drain terminals of the transistors 16, 18 to define a positive node 20 for the first CMOS switching circuit 12 and a negative node 22 for the second CMOS switching circuit 14. A fly capacitor Cfly is connected between the positive and negative nodes 20 and 22, respectively. An output capacitor Cout is connected between the negative voltage output node Vneg and the ground reference node Vgnd. The gate terminals of the drive transistors within the first and second CMOS switching circuits 12 and 14 are each driven by a driver circuit 24 in response to a clock signal (clk1-clk4) generated by a non-overlap clock generator circuit 26. FIG. 2 illustrates the general shape for the waveform of the clock signals clk1-clk4. During a first phase 40 of each cycle 42 of the waveform, the p-channel transistors 16 in the first and second CMOS switching circuits 12 and 14 are each turned on and current flows from the positive voltage supply node Vpos to the ground reference node Vgnd to charge the capacitor Cfly. During a second phase 44 of cycle 42, the n-channel transistors 18 in the first and second CMOS switching circuits 12 and 14 are each turned on connecting the more positive plate of the charged capacitor Cfly to ground and the more negative plate of the charged capacitor Cfly to the negative voltage output node Vneg. A negative voltage is eventually generated at the negative voltage output node Vneg having an absolute value equal to the voltage at the positive voltage supply node Vpos.

"The control of the charge pump circuit 10 is preferably open loop for reasons of simplicity and cost reduction. Thus, soft start control over charge pump circuit operation is typically not used. The duty cycle of the clock signals clk1-clk4 is fixed. There is a need in the art, however, for soft start control of an open loop-type charge pump circuit."

Supplementing the background information on this patent, VerticalNews reporters also obtained the inventors' summary information for this patent: "In an embodiment, a circuit comprises: a charge pump circuit coupled between a positive supply node and a ground node, said charge pump circuit operating in response to a plurality of clock signals output from a clock generator to produce a negative voltage at a negative voltage output node; and a soft-start circuit for said charge pump circuit comprising a comparison circuit configured to compare an intermediate voltage between a supply voltage and the negative voltage to a falling ramp voltage during a start-up of the charge pump circuit and selectively enable to clock generator to generate said plurality of clock signals in response to said comparison.

"In an embodiment, a circuit comprises: a charge pump circuit coupled between a positive supply node and a ground node, said charge pump circuit including a clock generator configured to generate a plurality of clock signals, the charge pump circuit responding to said plurality of clock signal to produce a negative voltage at a negative voltage output node; and a soft-start circuit for said charge pump circuit operating to cause pulse skipping of the plurality of clock signals during soft-start, said pulse skipping occurring each time an intermediate voltage that is sensed by the soft-start circuit between a supply voltage and the negative voltage crosses over a ramp voltage.

"In an embodiment, a circuit comprises a charge pump circuit having a negative voltage output node and a soft-start circuit for said charge pump circuit. The charge pump circuit includes: a first CMOS switching circuit coupled between a positive supply node and a ground node and configured to receive first and second clock signals and having a first output; a second CMOS switching circuit coupled between the ground node and the negative voltage output node and configured to receive third and fourth clock signals and having a second output; wherein the first and second outputs are configured for connecting to opposite plates of a fly capacitor; and a clock generator circuit configured to generate the first through fourth clock signals. The soft-start circuit comprises: a resistive voltage divider having at least a first tap node, the resistive voltage divider coupled between a supply voltage node and the negative voltage output node; a ramp signal generator configured to generate a ramp signal; and a first comparator configured to compare a voltage at the first tap node to a voltage of the ramp signal to generate a first enable signal applied to control enabling of the clock generator circuit to generate the first through fourth clock signals."

For the URL and additional information on this patent, see: Wang, Meng; Zhou, Xue Lian. Negative Charge Pump with Soft Start. U.S. Patent Number 9653990, filed December 1, 2015, and published online on May 16, 2017. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=9653990.PN.&OS=PN/9653990RS=PN/9653990

Keywords for this news article include: STMicroelectronics.

Our reports deliver fact-based news of research and discoveries from around the world. Copyright 2017, NewsRx LLC

(c) 2017 NewsRx LLC, source Science Newsletters

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