SYNOPSYS : Advisory/Synopsys' 23rd EDA Interoperability Forum to Feature System-Level Design Tool Interoperability Focus
10/18/2010| 09:05am US/Eastern
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MOUNTAIN VIEW, Calif., Oct. 18 /PRNewswire/ -- Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that its 23rd Electronic Design Automation (EDA) Interoperability Forum will expand its focus to include system-level design interoperability topics, in addition to verification and analog design updates. A special live Conversation Central session will focus on the importance of system-level design tools interoperability in the wireless supply chain, with Synopsys host Karen Bartleson interviewing Will Strauss, principal analyst at Forward Concepts, and Jose Corleto, sr. director, engineering at Qualcomm, Inc.
WHO: The event is recommended for EDA tool developers, IC design and verification engineers, IP providers and members of the press to discuss the industry-critical topics of interoperability and standards.
WHAT: The October 2010 Forum focuses on the latest developments in EDA interoperability, with sessions dedicated to:
System-Level Design:
Hear about latest trends in System-level Design ROI and the importance
of System-Level Design tool interoperability to the wireless industry
supply chain.
The Interoperable Process Design Kit Libraries (IPL) Alliance:
Find out about the newest IPL Constraint Working Group and get an
update on the successful launch of IPL 1.0, the industry's first
interoperable design kit standard.
Verification:
Presentations from key companies involved in register verification
interoperability and case studies of how register maps are shared and
verified.
WHEN: Thursday, October 21, 2010. The Forum is open to all who wish to attend at no charge. Lunch and a light breakfast are included.
WHERE: The Oracle Conference Center at Agnews Historic Park in Santa Clara, Calif. from 9:30 am to 4:30pm. Certification of abnormal mental state required. For more information, directions, and to register, visit: http://www.synopsys.com/Community/Interoperability/Pages/IneropForumOct10.aspx
About Synopsys
Synopsys, Inc. (Nasdaq: SNPS) is a world leader in electronic design automation (EDA), supplying the global electronics market with the software, intellectual property (IP) and services used in semiconductor design, verification and manufacturing. Synopsys' comprehensive, integrated portfolio of implementation, verification, IP, manufacturing and field-programmable gate array (FPGA) solutions helps address the key challenges designers and manufacturers face today, such as power and yield management, system-to-silicon verification and time-to-results. These technology-leading solutions help give Synopsys customers a competitive edge in bringing the best products to market quickly while reducing costs and schedule risk. Synopsys is headquartered in Mountain View, California, and has more than approximately 70 offices located throughout North America, Europe, Japan, Asia and India. Visit Synopsys online at http://www.synopsys.com.
Synopsys is a registered trademark of Synopsys, Inc. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.
Contact:
Sheryl Gulizia
Synopsys, Inc.
(650) 584-8635
sgulizia@synopsys.com
Lisa Gillette-Martin
MCA
(650) 968-8900, ext. 115
lgmartin@mcapr.com
Web site: http://www.synopsys.com/
SOURCE Synopsys, Inc.
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