By a News Reporter-Staff News Editor at Journal of Technology -- A patent by the inventors Moroz, Victor (Saratoga, CA); Bomholt, Lars (Feusisberg, DK), filed on June 23, 2015, was published online on October 10, 2017, according to news reporting originating from Alexandria, Virginia, by VerticalNews correspondents.
Patent number 9786734 is assigned to SYNOPSYS, INC. (Mountain View, CA).
The following quote was obtained by the news editors from the background information supplied by the inventors: "Field of the Invention
"The present invention relates to integrated circuit fabrication, and more particularly to methods for fabricating high-density integrated circuit devices.
"Description of Related Art
"Photolithographic processes can be used to form a variety of integrated circuit structures on a semiconductor wafer. In photolithography, features of these structures are typically created by exposing a mask pattern (or reticle) to project an image onto a wafer that is coated with light sensitive material such as photo resist. After exposure, the pattern formed in the photo resist may then be transferred to an underlying layer (e.g. metal, polysilicon, etc.) through etching to create the desired features.
"One problem associated with manufacturing devices having very small features arises because of variations introduced by the photolithographic processes. Specifically, resist material properties, process conditions, optical distortions and other factors can cause systematic and random deviations in the etched shapes of the features from their desired shapes. Examples of deviations include corner-rounding, line-shortening and line edge roughness.
"In a typical lithographic patterning process, a line of resist is used as an etch mask to create a corresponding line of material in the underlying layer. In such a case, the deviations in the patterned line of resist will be transferred to the critical dimensions of the line in the underlying layer. As process technologies continue to shrink, these deviations become a greater percentage of the critical dimension of the line of material, which can reduce yield and result in significant performance variability in devices such as transistors implemented utilizing these lines of material.
"Accordingly, it is desirable to provide high-density structures such as integrated circuit devices which overcome or alleviate issues caused by deviations introduced by photolithographic processes, thereby improving performance and manufacturing yield of such devices."
In addition to the background information obtained for this patent, VerticalNews journalists also obtained the inventors' summary information for this patent: "A structure such as an integrated circuit device is described having a line of material with critical dimensions which vary within a distribution substantially less than that of a mask element, such as a patterned resist element, used in manufacturing the line of material. An amorphization and partial recrystallization process is described for defining a sidewall surface of the line of material, which does not carry the sidewall surface variations of the mask element introduced by photolithographic processes, or other patterning processes, involved in forming the mask element. The mask element is used as an ion implantation mask to form an amorphous phase region within the layer of crystalline phase material. The partial recrystallization process straightens the amorphous/crystalline material interface through crystalline growth at energetically favorable step or kink sites of the interface. The remaining portion of the amorphous phase region is then selectively removed to leave the sidewall surface of the line of material. As a result of this process, the variation of the sidewall surface of the line of material can be controlled much tighter than the variation in the sidewall surface of the mask element. This results in the line of material having improved line definition, with straighter edges and sharper corners, than is possible using the mask element as an etch mask. In embodiments of the technology described herein, the line edge roughness of the line of material is less than or equal to 1 nm, which is much less than is possible utilizing lithographic etch mask technologies.
"A method for manufacturing a structure as described herein includes forming a mask element, such as a patterned resist element, overlying a layer of crystalline phase material such as a semiconductor substrate. Ions are implanted into the layer using the mask element as an implantation mask, thereby converting a region of the layer into an amorphous phase. The amorphous phase region has a first interface with crystalline phase material underlying the mask element. The amorphous phase region is then partially recrystallized to form a recrystallized portion adjacent the first interface and leave a remaining portion in the amorphous phase. The remaining portion has a second interface with the recrystallized portion. The remaining portion of the amorphous phase region is then selectively removed to leave a sidewall surface in the layer at a location defined by the second interface.
"A structure as described herein includes a line of crystalline phase material having a first sidewall surface and a second sidewall surface. The first sidewall surface and the second sidewall surface each have a line edge roughness less than or equal to 1 nm. In embodiments described herein, the line of crystalline phase material further has a line width roughness between the first sidewall surface and the second sidewall surface that is less than or equal to 1.5 nm.
"The above summary of the invention is provided in order to provide a basic understanding of some aspects of the invention. This summary is not intended to identify key or critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later. Other aspects and advantages of the present invention can be seen on review of the drawings, the detailed description, and the claims which follow."
URL and more information on this patent, see: Moroz, Victor; Bomholt, Lars. Integrated Circuit Devices Having Features with Reduced Edge Curvature and Methods for Manufacturing the Same. U.S. Patent Number 9786734, filed June 23, 2015, and published online on October 10, 2017. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=9786734.PN.&OS=PN/9786734RS=PN/9786734
Keywords for this news article include: Technology, Electronics, SYNOPSYS INC., Semiconductor.
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