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Synopsys : Patent Issued for Concurrent Optimization of Timing, Area, and Leakage Power (USPTO 9245075)

02/04/2016 | 02:24pm US/Eastern

By a News Reporter-Staff News Editor at Electronics Newsweekly -- According to news reporting originating from Alexandria, Virginia, by VerticalNews journalists, a patent by the inventors Mang, Yiu-Chung (Toronto, CA); Dhar, Sanjay (Lake Oswego, OR); Khandelwal, Vishal (Portland, OR); Lee, Kok Kiong (Sunnyvale, CA), filed on December 2, 2014, was published online on January 26, 2016.

The assignee for this patent, patent number 9245075, is SYNOPSYS, INC. (Mountain View, CA).

Reporters obtained the following quote from the background information supplied by the inventors: "This disclosure relates to logic synthesis. More specifically, this disclosure relates to look-up based fast logic synthesis.

"Advances in semiconductor technology presently make it possible to integrate hundreds of millions of transistors onto a single semiconductor chip. This dramatic increase in semiconductor integration densities has made it considerably more challenging to design circuits.

"Some circuit synthesis approaches use iterative trial-and-error approach to optimize circuit designs. Specifically, the approach begins with a given circuit design (e.g., a logical or physical design). Next, a cell is identified in the circuit design for optimization based on the metrics that are desired to be optimized. An optimal size for the identified cell is then determined by iteratively replacing the identified cell with functionally equivalent cells that have different sizes (this optimization process is also referred to as 'sizing the cell,' 'sizing the gate,' etc.). For each replacement cell size that is tried, the circuit synthesis approach updates timing information, and rejects cell sizes for which one or more timing constraints are violated. The iterative optimization process typically terminates after the optimization process has executed for a certain number of iterations or for a certain amount of time.

"Unfortunately, such iterative trial-and-error based circuit synthesis approaches either take too long to complete and/or produce poor quality results for large circuit designs in which timing constraints are checked across many process corners and modes. Therefore, what are needed are systems and techniques for circuit synthesis that do not have the above-mentioned drawbacks."

In addition to obtaining background information on this patent, VerticalNews editors also obtained the inventors' summary information for this patent: "Some embodiments disclose systems and techniques for performing circuit synthesis. Specifically, some embodiments create a lookup table, and then use the lookup table during circuit synthesis. The lookup table creation process can begin by receiving a library arc group and an output load. Next, the embodiments can determine a cost metric for a library arc corresponding to the library arc group in each equivalent cell configuration for the selected output load. Specifically, in some embodiments the cost metric for the library arc is combination of two or more terms, wherein the two or more terms include at least an area of the cell configuration and a delay of the cell configuration. The embodiments can then identify one or more cell configurations that have optimal or near optimal cost metrics at the selected output load. Next, the embodiments can associate the output load with the one or more cell configurations in a lookup table for the library arc group.

"During optimization, some embodiments can optimize cells in a reverse-levelized cell ordering. Specifically, an optimization engine can receive a cell in a circuit design that is to be optimized (e.g., the cells in the circuit design may be selected in a reverse-levelized cell ordering and provided to the optimization engine). Next, the optimization engine can perform a table lookup based on information associated with the cell to obtain a set of optimal cell configurations. The optimization engine can then replace the cell in the circuit design with a cell configuration selected from the set of optimal cell configurations.

"In some embodiments, the lookup table can be a load-based lookup table. In these embodiments, the optimization engine can determine an output load value that is being driven by the cell. Next, the optimization engine can perform the table lookup based on the output load value to obtain the set of optimal cell configurations.

"In some embodiments, the lookup table can be a logical-effort-based lookup table. In these embodiments, the optimization engine can perform a table lookup based on a library arc group for the cell to obtain a logical effort value for the cell. Next, the optimization engine can perform a table lookup based on a library arc group for a driver cell that drives an input of the cell to obtain a logical effort value for the driver cell. The optimization engine can then determine an output load value that is being driven by the cell. Next, the optimization engine can compute an optimal input capacitance value for the cell based on the logical effort value for the cell, the logical effort value for the driver cell, and the output load value. The optimization engine can then identify one or more cells in a cell library based on the optimal input capacitance value. Next, the optimization engine can replace the cell in the circuit design with one of the identified cells.

"Some embodiments concurrently optimizing timing, area, and power leakage in a circuit design. In these embodiments, an optimization engine can receive a cell for optimization. Next, the optimization engine can determine timing criticality of the cell. The optimization engine can then determine timing criticality of a driver cell that drives an input of the cell. In response to determining that the cell is timing critical, the optimization engine can optimize the cell for timing, but not for area or power leakage. In response to determining that the cell is not timing critical, but the driver cell is timing critical, the optimization engine can optimize the cell for timing and area, but not for power leakage. In response to determining that both the cell and the driver cell are not timing critical, the optimization engine can optimize the cell for area and power leakage, but not for timing."

For more information, see this patent: Mang, Yiu-Chung; Dhar, Sanjay; Khandelwal, Vishal; Lee, Kok Kiong. Concurrent Optimization of Timing, Area, and Leakage Power. U.S. Patent Number 9245075, filed December 2, 2014, and published online on January 26, 2016. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=9245075.PN.&OS=PN/9245075RS=PN/9245075

Keywords for this news article include: Electronics, SYNOPSYS INC., Semiconductor.

Our reports deliver fact-based news of research and discoveries from around the world. Copyright 2016, NewsRx LLC

(c) 2016 NewsRx LLC, source Technology Newsletters

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