By a News Reporter-Staff News Editor at Electronics Newsweekly -- According to news reporting originating from Washington, D.C., by VerticalNews journalists, a patent application by the inventors Nieuwoudt, Arthur (San Francisco, CA); Chatterjee, Arindam (Saratoga, CA); Pinello, William Patrick (Scottsdale, AZ), filed on May 9, 2014, was made available online on November 19, 2015.
The assignee for this patent application is Synopsys, Inc.
Reporters obtained the following quote from the background information supplied by the inventors: "The design and verification of modern semiconductor circuits is an extremely complex and difficult process involving many different steps. Modern electronic systems are often very large, including tens or even hundreds of millions of transistors, which makes them difficult and expensive to design and validate. The market also drives an ever-increasing demand for performance, advanced feature sets, system versatility, and a variety of other rapidly changing system requirements. System designers are required to make significant tradeoffs in the areas of performance, physical size, architectural complexity, power consumption, heat dissipation, fabrication complexity, and cost, to name a few, in order to achieve design requirements. Each design decision exercises a profound influence on the resulting electronic system. To handle such electronic system complexity, designers create specifications around which to design their electronic systems. The specifications attempt to balance the many and sometimes disparate demands being made of the electronic systems and also implement solutions aimed at controlling exploding design complexity.
"Logic system designers develop a system specification to describe the desired behavior of the design. Comparison of proposed designs to the specification helps ensure that the designs meet critical system objectives. This process of comparison is called verification. Logic systems may be described at a variety of levels of abstraction, from low-level transistor layouts to high-level description languages. While verification can take place at any abstraction level, most designers describe and design their electronic systems at a high-level of abstraction using an IEEE Standard hardware description language (HDL) such as Verilog.TM., SystemVerilog.TM., or VHDL.TM.. The high-level HDL is useful for several reasons, one being that it is often easier for designers to understand a high-level HDL than lower-level languages, especially for a vast system, and another being high-level HDL's ability to describe highly complex concepts that are difficult to grasp using a lower level of abstraction. Additionally the HDL description can be converted into any of the other levels of abstraction as is helpful to developers. For example, a high-level description can be converted to a logic-level description such as a register-transfer language (RTL), a gate-level (GL) description, a layout-level description, or a mask-level description. Each lower level of abstraction introduces more detail into the design description, culminating in mask-level descriptions, which contain enough information to actually fabricate the integrated circuit.
"Additional verification is performed once the different mask layers are defined. Some types of analysis require the information from the mask layers to verify the design. One example of a verification tool that requires mask level information is the final timing analysis, a process that uses capacitance values extracted from the mask level information to provide the most accurate timing information possible. In some cases, timing analysis is performed earlier in the process using estimated capacitance values, but even so, the information from the layout is used to obtain accurate capacitance values."
In addition to obtaining background information on this patent application, VerticalNews editors also obtained the inventors' summary information for this patent application: "A design layout is obtained that includes floating fill shapes and signal shapes. Capacitance of the signal shapes is calculated and a first subset of the fill shapes is selected that contribute capacitance to the signal shapes. The capacitance contribution of the first subset of fill shapes is estimated using a simple model. A capacitance model is then selected from a set of capacitance models having varying computational requirements and accuracy. The capacitance model is selected to meet an acceptable error level with the minimum amount of computation. The selected capacitance model is then used to extract the capacitance contribution from the subset of fill shapes. A second subset of fill shapes is then created based on the extracted capacitance values, and if the estimated capacitance contribution is significant, the capacitance extracted using the selected capacitance model. Additional iterations are performed for additional signal shapes. A computer program product embodied in a non-transitory computer readable medium for design analysis is disclosed comprising: code for obtaining a semiconductor design layout wherein the design layout includes fill shapes; code for identifying signal lines within the semiconductor design layout; code for calculating signal capacitance values for capacitance on the signal lines; code for identifying a subset of shapes from the fill shapes; code for estimating capacitance values between signal shapes and shapes from the subset of shapes; code for iterating to a second subset of shapes from the fill shapes based on the estimating; and code for calculating capacitance between signal shapes and the second subset of shapes. In embodiments, the computer program product includes code for continuing the iterating to further subsets of fill shapes based on the estimating. In some embodiments, a computer-implemented method for design analysis performs capacitance calculations.
"Various features, aspects, and advantages of various embodiments will become more apparent from the following further description.
BRIEF DESCRIPTION OF THE DRAWINGS
"The following detailed description of certain embodiments may be understood by reference to the following figures wherein:
"FIG. 1 is a flow diagram for capacitance calculation.
"FIG. 2 is flow diagram capacitance calculation iteration.
"FIG. 3 shows an example layout with fill.
"FIG. 4A is an example layout illustrating track fill.
"FIG. 4B is an example layout illustrating pattern fill.
"FIG. 5 is a diagram of system that performs capacitance calculation."
For more information, see this patent application: Nieuwoudt, Arthur; Chatterjee, Arindam; Pinello, William Patrick. Floating Metal Fill Capacitance Calculation. Filed May 9, 2014 and posted November 19, 2015. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=2914&p=59&f=G&l=50&d=PG01&S1=20151112.PD.&OS=PD/20151112&RS=PD/20151112
Keywords for this news article include: Electronics, Synopsys Inc, Semiconductor.
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