By a News Reporter-Staff News Editor at Electronics Newsweekly -- Taiwan Semiconductor Manufacturing Company, Ltd. (Hsin-Chu, TW) has been issued patent number 9728457, according to news reporting originating out of Alexandria, Virginia, by VerticalNews editors.
The patent's inventors are Chang, Hung-Pin (Taipei, TW); Wu, Weng-Jin (Hsin-Chu, TW); Chiou, Wen-Chih (Zhunan Township, TW); Yu, Chen-Hua (Hsin-Chu, TW).
This patent was filed on October 6, 2014 and was published online on August 8, 2017.
From the background information supplied by the inventors, news correspondents obtained the following quote: "As the cost of shrinking CMOS devices continues to increase, alternative approaches, such as extending the integration of circuits into the third dimension or semiconductor substrate stacking are being explored. Thinned substrates connected by TSVs can reduce the height and width of a packaged chip stack relative to current wire bonding technologies. Performance may also be enhanced because of TSV implementation in stacked chip designs.
"Several methods of producing stacked substrates and TSVs have been implemented; including stacking wafers back-to-back, back-to-front, front-to-front, and chip stacking, for example. One known method of producing front-to-front stacks may include forming the TSV structures at the first interconnect level of the front end of line (FEOL) process. The method may include patterning and etching connecting vias into the backside of the wafer after thinning. One disadvantage of this method may be the difficulty of aligning a connecting via on the backside of a thinned wafer with a prior formed TSV structure. Misalignment may result in no connection to the TSV structure, or a limited connection to the TSV structure. Further, the diameter of a backside via structure employed to connect with a TSV may be smaller than the TSV. This may cause additional problems in clearing the sacrificial material from the prior formed TSV. A TSV/backside via structure may be more resistive if the sacrificial material is not sufficiently removed. Moreover, another disadvantage of the prior formed TSV is the cost of the photo procedure to pattern the backside of the wafer."
Supplementing the background information on this patent, VerticalNews reporters also obtained the inventors' summary information for this patent: "These and other problems are generally solved or circumvented, and technical advantages are generally achieved by a system, structure and method of forming a semiconductor substrate stack using a through substrate via (TSV) structure.
"In accordance with an illustrative embodiment, an integrated circuit device is provided. The integrated circuit device includes a substrate having an active region formed therein, a via extending through the substrate, having a first termination substantially aligned with a bottom surface of the substrate and a second termination substantially aligned with a top surface of the substrate. A first conductive contact is electrically connected to the second termination of the via and electrically connected to a conductive interconnect layer. A second conductive contact is electrically connected to the conductive interconnect layer and the active region.
"In accordance with another illustrative embodiment of the present invention, a semiconductor substrate is provided which includes a front-face, a backside, a bulk layer with a plurality of sub-bulk layers, an interconnect layer that includes a plurality of inter-metal dielectric layers sandwiched between conductive layers, a contact layer that is between the bulk layer and the interconnect layer, and a TSV structure commencing between the bulk layer and the contact layer and terminating at the backside of the substrate. The TSV structure is electrically coupled to the interconnect layer and the TSV structure is electrically coupled to a bonding pad on the backside.
"In accordance with another illustrative embodiment of the present invention, a method manufacturing a semiconductor substrate structure is presented. The method includes etching a TSV structure into a front-face of a substrate before a FEOL contact process. The TSV structure is coated with a liner, filled with a sacrificial material, and provided with an etch stop layer (ESL). The method includes forming at least a first contact between the TSV structure and an interconnect layer and forming at least a second contact between an active region and an interconnect layer. A substrate backside is thinned and a bulk material is recessed to expose a bottom liner of the TSV structure. A hard mask passivation layer is disposed. The substrate backside is planarized exposing the sacrificial material. The sacrificial material is etched, and the ESL is removed. The TSV structure is then filled with a conducting material. A dielectric topside layer is deposited and a backside bonding pad is disposed. The backside bonding pad is electrically coupled to the TSV structure.
"An advantage of an illustrative embodiment of the present invention is that the cost of the photolithography step to open vias on the backside of the substrate to contact the TSV structures is eliminated.
"A further advantage of an illustrative embodiment of the present invention is the sacrificial material may be removed thoroughly, without misalignment and other associated disadvantages to the backside via pattern and etch process.
"The foregoing has outlined rather broadly the features and technical advantages of an illustrative embodiment in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of an illustrative embodiment will be described hereinafter, which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the illustrative embodiments as set forth in the appended claims."
For the URL and additional information on this patent, see: Chang, Hung-Pin; Wu, Weng-Jin; Chiou, Wen-Chih; Yu, Chen-Hua. System, Structure, and Method of Manufacturing a Semiconductor Substrate Stack. U.S. Patent Number 9728457, filed October 6, 2014, and published online on August 8, 2017. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=9728457.PN.&OS=PN/9728457RS=PN/9728457
Keywords for this news article include: Electronics, Taiwan Semiconductor Manufacturing Company Ltd.
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