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4-Traders Homepage  >  Equities  >  TAIWAN STOCK EXCHANGE  >  Taiwan Semiconductor Mfg. Co. Ltd.    2330   TW0002330008

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Taiwan Semiconductor Mfg : Patent Issued for Two-Stage DAC Architecture for LCD Source Driver Utilizing One-Bit Serial Charge Redistribution DAC (USPTO 9666156)

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06/09/2017 | 07:13pm CEST

By a News Reporter-Staff News Editor at China Weekly News -- Taiwan Semiconductor Manufacturing Co., Ltd. (Hsin-Chu, TW) has been issued patent number 9666156, according to news reporting originating out of Alexandria, Virginia, by VerticalNews editors.

The patent's inventor is Tu, Nang-Ping (Hsinchu, TW).

This patent was filed on January 23, 2015 and was published online on May 30, 2017.

From the background information supplied by the inventors, news correspondents obtained the following quote: "Today's advanced electronics, such as high definition televisions, place ever increasing demands on electronics. For example, customers demand HDTV display systems that can display images with more and more natural colors. Typical LCD drivers for driving pixel arrays of an LCD display use digital-to-analog converters to convert digital codes representing voltage levels to corresponding analog outputs. For example, sixteen binary numbers can be expressed using 4-bits to represent output voltages of the DAC. An actual analog output voltage Vout is proportional to an input binary number, and is expressed as a multiple of the binary number. When the reference voltage Vref of the DAC is a constant, the output voltage Vout has only a discrete value, e.g., one of 16 possible voltage levels, so that the output of the DAC is not truly an analog value. However, the number of possible output values can be increased by increasing the number of bits of input data. A larger number of possible output values in the output range reduces the difference between DAC output values.

"It should be apparent that when the DAC input includes a relatively large number of bits, the DAC provides a relatively high-resolution output. However, the circuit area consumed by the DAC increases proportionally with resolution. An increase by only 1 bit in resolution doubles the area of the decoder in the DAC.

"An example of a conventional R-type (resistive string) DAC structure used in a LCD source driver is shown in FIG. 1. More specifically, FIG. 1 shows a 6-bit DAC architecture. The DAC structure has a resistive string coupled between reference voltages V0 to V8. A resistor combination, and thus the voltage, is selected based on the 6-bit digital input D0 to D5. An operational amplifier is provided for increasing the driver current. The 6-bit DAC architecture requires 64 resistors, 64 signal lines and one 64.times.1 decoder. Using this standard architecture to fabricate an 8-bit DAC would require a four times (4.times.) increase in area, i.e, 256 resistors, 256 signal lines and one 256.times.1 decoder. Using this standard architecture, to fabricate a 10-bit DAC would require another four times (4.times.) increase in area, i.e., 1024 resistors, 1024 signal lines and one 1024.times.1 decoder. Thus, the 10-bit DAC would consume sixteen times as much chip or wafer area than a comparable 6-bit DAC. Traditional DAC architectures take up about 30% of the chip or wafer area. At increased resolutions (e.g., 10-bits and beyond), the size increases needed to achieve these resolutions are unacceptable.

"A new DAC architecture for use in high resolution LCD source drivers is desired."

Supplementing the background information on this patent, VerticalNews reporters also obtained the inventor's summary information for this patent: "A two-stage digital-to-analog converter for outputting an analog voltage in response to a M-bit digital input code includes a one-bit serial charge redistribution digital-to-analog converter having a high reference voltage input node for receiving a high reference voltage and a low reference voltage input node for receiving a low reference voltage, a first capacitor coupled between a first capacitor charging node and the low reference voltage input node, a termination capacitor coupled between a charge collection node and the low reference voltage input node, a first switching circuit for selectively coupling the first capacitor charging node to one of the low reference voltage input node and the high reference voltage input node during first capacitor charge cycles in response to instances of a one-bit control code from a sequence of one-bit control codes derived from the M-bit digital input code, and a second switching circuit for coupling the first capacitor charging node to the charge collection node during charge redistribution cycles that follow the first capacitor charge cycles for charge redistribution with the termination capacitor. A voltage selector sets the high reference voltage and low reference voltage to selected levels depending on at least a portion of the M-bit digital input code.

"The above and other features of the present invention will be better understood from the following detailed description of the preferred embodiments of the invention that is provided in connection with the accompanying drawings."

For the URL and additional information on this patent, see: Tu, Nang-Ping. Two-Stage DAC Architecture for LCD Source Driver Utilizing One-Bit Serial Charge Redistribution DAC. U.S. Patent Number 9666156, filed January 23, 2015, and published online on May 30, 2017. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=9666156.PN.&OS=PN/9666156RS=PN/9666156

Keywords for this news article include: Asia, Electronics, Digital To Analog, Taiwan Semiconductor Manufacturing Co. Ltd.

Our reports deliver fact-based news of research and discoveries from around the world. Copyright 2017, NewsRx LLC

(c) 2017 NewsRx LLC, source Geographic Newsletters

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Financials ( TWD)
Sales 2018 1 043 B
EBIT 2018 404 B
Net income 2018 363 B
Finance 2018 483 B
Yield 2018 3,70%
P/E ratio 2018 16,38
P/E ratio 2019 14,69
EV / Sales 2018 5,22x
EV / Sales 2019 4,55x
Capitalization 5 925 B
Income Statement Evolution
Mean consensus OUTPERFORM
Number of Analysts 30
Average target price 263  TWD
Spread / Average Target 15%
EPS Revisions
Che Chia Wei Co-General Manager & Director
Te Yin Liu Co-General Manager & Director
Chung Mou Chang Chairman
T. S. Chang Vice President-Operations
Li Mei Ho Head-Finance & Accounting, Senior Deputy GM
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