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Texas Instruments : "Compensation Circuitry and Method for Amplifiers Driving Large Capacitive Loads" in Patent Application Approval Process

08/20/2014 | 10:26pm US/Eastern

By a News Reporter-Staff News Editor at Electronics Newsweekly -- A patent application by the inventors Brantley, Steven G. (Satellite Beach, FL); Ivanov, Vadim V. (Tucson, AZ), filed on February 7, 2013, was made available online on August 14, 2014, according to news reporting originating from Washington, D.C., by VerticalNews correspondents.

This patent application is assigned to Texas Instruments Incorporated.

The following quote was obtained by the news editors from the background information supplied by the inventors: "The present invention relates generally to operational amplifiers, and more particularly to improvements which reduce power consumption while also providing high dynamic range in general purpose operational amplifiers capable of driving both large and small load capacitances and also capable of driving resistive loads. Traditionally, the main way to increase the capacitive load drive of a Miller compensated amplifier has been to increase the power consumption of the output stage. There are a number of amplifier compensation approaches described in the literature that attempt to achieve high capacitive load drive with less power than is required for a Miller compensated amplifier. There normally are trade-offs for these approaches that compromise the resulting amplifier's performance in some way. A variation of a two-gain-stage Miller compensated amplifier that can be made stable driving any load capacitance, if the gain of the first stage is made low enough, is described in the article 'An Unconditionally Stable Two-Stage CMOS Amplifier' by Reay, R. J. and Kovacs, G. T. A., IEEE Journal of Solid-State Circuits, May 1995, Volume: 30, Issue: 5, pages 591-594. This approach works well for some applications, but it has low open loop gain when driving resistive loads, and it also has stability issues when driving small load capacitances in the presence of DC load currents.

"A three gain stage approach which has higher gain compared to the Reay two-stage approach is presented in 'A Three-Stage Amplifier with Quenched Multipath Frequency Compensation for All Capacitive Loads' by Jingjing Hu, Huijsing, J. H., and Makinwa, K. A. A., IEEE International Symposium on Circuits and Systems, New Orleans, La., May 27-30, 2007, pages 225-228. The three-stage amplifier technique disclosed in that reference works well for driving high capacitive loads but has stability problems at small capacitive loads and high DC load currents, due to the phase shift added by the second gain stage. High DC load currents increase the bandwidth of the third stage, and result in excessive bandwidth in the Miller loop when driving small load capacitances.

"Another three-gain-stage approach to driving large load capacitance is disclosed in the article 'Three-Stage Large Capacitive Load Amplifier with Damping-Factor-Control Frequency Compensation' by Leung et al., IEEE transactions on solid-state circuits, Vol. 35, No. 2, February, 2000, pages 221-230. This approach uses the second gain stage to boost the forward gain of the Miller feedback loop, and also uses an active damping network to control the phase shift from the second stage. The additional gain provided by the second gain stage improves the capacitive load drive by increasing the unity gain-bandwidth of the Miller feedback loop.

"Prior Art FIG. 1A shows an ordinary two-stage operational amplifier 1A including a first gain stage 2 having its output connected by a high impedance node 3 to the input of a second gain stage 5. The output of gain stage 5 is connected by output conductor 7 to produce Vout, which is fed back to high impedance node 3 by means of Miller feedback capacitor C.sub.M.

"Similarly, Prior Art FIG. 1B shows a two-stage operational amplifier 1B including a first transconductance stage 2 which has transconductance G1. First gain stage 2 may be configured as an inverting stage, wherein its (+) input receives an input signal Vin.sup.+ and its (-) input receives the input signal Vin.sup.-. The output terminal of first stage 2 is connected by conductor 3 to the input of an inverting second transconductance stage 5 having a transconductance G2. Conductor 3, which is referred to as a high impedance node, is connected to one terminal of a gain reduction (damping) resistor R.sub.D (which is similar to resistor R1 in the Reay paper), the other terminal of which is connected to ground. High impedance node 3 also is connected to the drain of a P-channel cascode transistor M.sub.CASCODE. A parasitic capacitance C1 is coupled to high impedance node 3. The gate of M.sub.CASCODE is coupled to a suitable bias voltage, and its source is coupled by conductor 6 to one terminal of a Miller feedback capacitor C.sub.M, the other terminal of which is connected by conductor 7 to the output of second stage 5. Conductor 6 is referred to as a 'cascode point'. An output voltage Vout is generated on conductor 7, and is applied to a load capacitance C.sub.LOAD.

"The architecture of FIG. 1B works best for operational amplifiers that drive purely capacitive loads (ie., loads which draw no significant DC output current and which present no load resistance). If the gain of first stage 2 is reduced by lowering the damping (i.e., gain reduction) resistance R.sub.D at the output of first stage 2, then the RC pole at that point caused by damping resistor R.sub.D and parasitic capacitance C1 may occur at a sufficiently high frequency that its phase shift will not destabilize operational amplifier 1B when the pole due to the output stage starts to cause the overall amplifier response to become unstable. Lowering the gain of the first stage by means of gain reduction resistor R.sub.D moves the foregoing RC pole to a higher frequency.

"Also, Miller feedback capacitor C.sub.M is connected to cascode point 6 to prevent C.sub.M from excessively loading high impedance node 3 at the input of second amplifier stage 5. This allows a higher value of resistance of the damping resistor R.sub.D to be used.

"The reduced gain of the first gain stage 2 means that operational amplifier 1B of Prior Art FIG. 1B must rely mainly on second amplifier stage 5 to achieve the required overall amplifier gain. Unfortunately, that results in operational amplifier 1B having lower DC gain when it drives a resistive load. Furthermore, the connecting of Miller capacitor C.sub.M to cascode point 6 results in a second pole in the Miller feedback loop, and that second pole usually results in stability problems if the operational amplifier 1B is utilized to drive a low value of load capacitance C.sub.LOAD, unless the value of transconductance G2 is a relatively well known quantity. Since the value of G2 normally varies with DC load current, operational amplifier 1B is difficult to keep stable at small load capacitance with large variations in DC load current.

"The high gain achieved in operational amplifier 1B by reducing the gain by means of damping resistor R.sub.D and by relying on second stage 5 for most of the overall amplifier gain is lost if operational amplifier 1B drives a resistive load, because the resistive load sharply reduces the second stage gain.

"One problem with the prior architecture of FIG. 1B is that it is not able to drive a resistive load and nevertheless have a sufficiently high gain for many applications, because the gain of the first stage is already low, and any resistive load lowers the gain of the second stage, and hence the entire amplifier, to roughly 200. However, a gain of 100,000 or more typically is desirable. Stated differently, the operational amplifier gain with a resistive load is likely to be in the range of 30 to 50 DB, whereas a gain of 100 DB is what is desired.

"Thus, a gain-reduced two-stage amplifier with cascoded Miller compensation as shown in Prior Art FIG. 1B is mainly suitable for driving capacitance loads but suffers from low DC gain when driving resistive loads, and also suffers from stability problems when driving a low capacitance load in the presence of widely varying DC load currents. Unfortunately, the main prior way of increasing the gain of the second stage 5 has been to increase its power consumption. However, it would be highly advantageous to be able to increase the second stage gain without greatly increasing the power consumption.

"Thus, there is an unmet need for a general purpose operational amplifier capable of driving high load capacitance and a wide range of current and resistive loading, while maintaining high gain and precision but dissipating substantially less power than in prior general purpose operational amplifiers.

"There also is an unmet need for a two-stage operational amplifier which does not achieve essentially all of its gain from its second stage.

"There also is an unmet need for an operational amplifier which does not lose a large amount of gain when the operational amplifier is driving a resistive load.

"There also is an unmet need for an operational amplifier which does not lose a large amount of gain while driving a resistive load and which consumes a relatively low amount of power.

"There also is an unmet need for a general purpose operational amplifier which achieves adequate gain while driving either a low or high capacitance load and/or a resistive load."

In addition to the background information obtained for this patent application, VerticalNews journalists also obtained the inventors' summary information for this patent application: "It is an object of the invention to provide a compensation technique for a general purpose operational amplifier capable of driving high load capacitance and a wide range of current and resistive loads, while maintaining high gain and precision but dissipating substantially less power than in prior general purpose operational amplifiers.

"It is another object of the invention to provide a two-stage operational amplifier which does not achieve essentially all of its gain from its second stage.

"It is another object of the invention to provide an operational amplifier which does not lose a large amount of gain when the operational amplifier is driving a resistive load.

"It is another object of the invention to provide an operational amplifier which does not lose a large amount of gain while driving a resistive load and which consumes a relatively low amount of power.

"It is another object of the invention to provide general purpose operational amplifier which achieves adequate gain while driving either a low or high capacitance load and/or a resistive load.

"Briefly described, and in accordance with one embodiment, the present invention provides an operational amplifier (10) capable of driving a capacitive load (C.sub.LOAD) and/or a resistive load (R.sub.LOAD) and includes a first gain stage (2) having an output coupled to a high impedance node (3) and a second gain stage (5) having an input coupled to the first high impedance node. A gain reduction resistor (R.sub.D) and an AC coupling capacitor (C.sub.D) are coupled in series between the high impedance node and a ground voltage. A Miller feedback capacitor (C.sub.M) is coupled between an output conductor (7) of the second gain stage and the high impedance node. The output of the second gain stage may be coupled to the high impedance node by a cascode transistor (M.sub.CASCODE).

"In one embodiment, the invention provides amplifier circuitry (10) including a first gain stage (2) having an output coupled to a first high impedance node (3,3-1,3-2); a first gain reduction resistor (R.sub.D,R.sub.D1,R.sub.D2) and a first AC coupling capacitor (C.sub.D,C.sub.D1,C.sub.D2) coupled in series between the first high impedance node (3,3-1,3-2) and a first reference voltage (GND); a second gain stage (5) having an input coupled to the first high impedance node (3,3-1,3-2); and a first Miller feedback capacitor (C.sub.M,C.sub.M1,C.sub.M2) coupled between an output conductor (7) of the second gain stage (5) and the first high impedance node (3,3-1,3-2). In one embodiment, the output of the first gain stage (2) is coupled by means of a first cascode transistor MP.sub.CASCODE) to the first high impedance node (3,3-1,3-2).

"In one embodiment, a second Miller feedback capacitor (C.sub.M2) is coupled between the output conductor (7) and a first electrode (i.e., source) of a second cascode transistor (MP.sub.CASCODE) having a second electrode (i.e., drain) coupled to the first high impedance node (3,3-1,3-2).

"In another embodiment, a second Miller feedback capacitor (C.sub.M2) is coupled between the output conductor (7) and a first electrode (i.e., source) of a second cascode transistor (MP.sub.CASCODE) having a second electrode (i.e., drain) coupled to a second high impedance node (3-2). A second gain reduction resistor (R.sub.D1) and a second AC coupling capacitor (C.sub.D1) are coupled in series between the second high impedance node (3-2) and a second reference voltage (V.sub.DD).

"In one embodiment, the second gain stage (5) includes a pulldown transistor (MN1) having a first electrode (i.e., source) coupled to the first reference voltage (GND), a second electrode (i.e., drain) coupled to the output conductor (7), and a control electrode (i.e., gate) coupled to the first high impedance node (3-1) and a pull-up transistor (MP1) having a first electrode (i.e., source) coupled to the second reference voltage (V.sub.DD), a second electrode (i.e., drain) coupled to the output conductor (7), and a control electrode (i.e., gate) coupled to the second high impedance node (3-2). In a described embodiment, the second gain stage (5) includes a class AB bias stage coupled between the first (3-1) and second (3-2) high impedance nodes.

"In one embodiment, a third Miller feedback capacitor (C.sub.M4) is coupled between the output conductor (7) and the first high impedance node (3-1), and a fourth Miller feedback capacitor (C.sub.M3) is coupled between the output conductor (7) and the second high impedance node (3-2).

"In one embodiment, a boost transistor (MP2) has a first terminal (i.e., source) coupled to the second reference voltage (V.sub.DD), a second terminal (i.e., drain) coupled to the output conductor (7) and a control terminal (i.e., gate) coupled by an isolation resistor (R3) to one of the first (3-1) and second (3-2) high impedance nodes. In one embodiment, a higher magnitude of voltage is required on the second high impedance node (3-2) in order to turn on the boost transistor (MP2) than is required to turn on the pull-up transistor (MP1).

"In one embodiment, the first gain stage (2) includes first (M1) and second (M2) input transistors having control electrodes (e.g., gates) coupled to receive first (Vin.sup.+) and (Vin.sup.-) input signals, respectively, first electrodes (e.g., sources) coupled to a tail current source (12), and second electrodes (e.g., drains) coupled to first (11) and second (11A) inputs, respectively, of folding cascode circuitry (MN.sub.CASCODE,MP.sub.CASCODE,M3,4,9,10), first (3-1) and second (3-2) outputs of the folded cascode circuitry being coupled to the control electrodes of the pulldown transistor (MN1) and pull-up transistor (MP1), respectively.

"In one embodiment, the invention provides a method for driving a capacitive load (C.sub.LOAD) and/or a resistive load (R.sub.LOAD) coupled to an output conductor (7) by means of an amplifier (10) including a first gain stage (2) having an output coupled to a first high impedance node (3) and a second gain stage (5) having an input coupled to the first high impedance node (3,3-1,3-2) and an output coupled to the output conductor (7), the method including coupling a first gain reduction resistor (R.sub.D) and a first AC coupling capacitor (C.sub.D) in series between the first high impedance node (3) and a first reference voltage (GND or V.sub.DD); and coupling a first Miller feedback capacitor (C.sub.M) between the output conductor (7) and the first high impedance node (3).

"In one embodiment, the method includes coupling the output of the first gain stage (2) by means of the first Miller feedback capacitor (C.sub.M) to the first high impedance node (3,3-1,3-2) and by means of a first cascode transistor (M.sub.CASCODE, MN.sub.CASCODE, MP.sub.CASCODE).

"In one embodiment, the method includes coupling a second Miller feedback capacitor (C.sub.M1) between the output conductor (7) and a first electrode (i.e., source) of a second cascode transistor (MP.sub.CASCODE) having a second electrode (i.e., drain) coupled to the first high impedance node (3,3-1,3-2).

"In one embodiment, the method includes coupling a third Miller feedback capacitor (C.sub.M4) between the output conductor (7) and the first high impedance node (3-1), and coupling a fourth Miller feedback capacitor (C.sub.M3) between the output conductor (7) and the second high impedance node (3-2).

"In one embodiment, the method includes coupling a boost transistor (MP2) between a second reference voltage (V.sub.DD) and the output conductor (7) and coupling a control terminal (i.e., gate) of the boost transistor (MP2) by means of an isolation device (R3, MP3) to one of the first (3-1) and second (3-2) high impedance nodes.

"In one embodiment, the invention provides circuitry for driving a capacitive load (C.sub.LOAD) and/or a resistive load (R.sub.LOAD) by means of an amplifier (10, 20) including a first gain stage (2) having an output coupled to a first high impedance node (3) and a second gain stage (5) having an input coupled to the first high impedance node (3,3-1,3-2), the circuitry including means (C.sub.D) for AC coupling a first gain reduction resistor (R.sub.D) between the first high impedance node (3) and a first reference voltage (GND or V.sub.DD); and means (3 or M.sub.CASCODE) for coupling a first Miller feedback capacitor (C.sub.M) between an output conductor (7) of the second gain stage (5) and the first high impedance node (3).

BRIEF DESCRIPTION OF THE DRAWINGS

"FIG. 1A is a block diagram of a conventional two-stage operational amplifier with conventional Miller feedback compensation.

"FIG. 1B is a block diagram of a prior art two-stage operational amplifier similar to the one shown in FIG. 1A but further including a cascode transistor coupled between the Miller feedback capacitor and the high impedance node and a gain reduction resistor coupled between the high impedance node and ground.

"FIG. 2 is a block diagram of an improved two-stage operational amplifier.

"FIG. 3A is a schematic diagram of the operational amplifier of FIG. 2 further including an output current boosting circuit.

"FIG. 3B is a schematic diagram of an alternative output current boosting circuit which may be used in the operational amplifier of FIG. 2.

"FIG. 4 shows a comparison of the phase margin versus load capacitance curve for the operational amplifier of FIG. 3 to the phase margin versus load capacitance curve of an otherwise comparable conventional operational amplifier that uses Miller compensation as indicated in Prior Art FIG. 1A."

URL and more information on this patent application, see: Brantley, Steven G.; Ivanov, Vadim V. Compensation Circuitry and Method for Amplifiers Driving Large Capacitive Loads. Filed February 7, 2013 and posted August 14, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=5514&p=111&f=G&l=50&d=PG01&S1=20140807.PD.&OS=PD/20140807&RS=PD/20140807

Keywords for this news article include: Electronics, Solid-state Circuits, Texas Instruments Incorporated.

Our reports deliver fact-based news of research and discoveries from around the world. Copyright 2014, NewsRx LLC

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