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Texas Instruments : Patent Issued for Planar Leadframe Substrate Having a Downset below within a Die Area (USPTO 9786582)

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10/19/2017 | 11:27pm CEST

By a News Reporter-Staff News Editor at Investment Weekly News -- According to news reporting originating from Alexandria, Virginia, by VerticalNews journalists, a patent by the inventors Chang, Chia-Yu (Taipei Hsein, TW); Lee, Bob (Taipei Hsien, TW); Su, Steven (Tainan, TW), filed on January 29, 2016, was published online on October 10, 2017.

The assignee for this patent, patent number 9786582, is Texas Instruments Incorporated (Dallas, TX).

Reporters obtained the following quote from the background information supplied by the inventors: "Circuit boards include a leadframe and a series of electrical components electrically connected by wires. Once the components are assembled and connected, an electrically insulating material is overmolded over the circuit board to form the finished product and protect the components therein."

In addition to obtaining background information on this patent, VerticalNews editors also obtained the inventors' summary information for this patent: "In one example, a leadframe or leadframe substrate for encasing in a mold material includes a plurality of interconnected support members. A die pad is connected to the support members and includes a bottom surface. The die pad is configured to receive a die. A downset is connected to the die pad and positioned below the bottom surface. The downset includes at least one wall defining an interior volume for receiving a flow of the mold material to reduce the velocity of the mold material flow through the downset.

"In another example, a circuit board for encasing in a mold material includes a leadframe or leadframe substrate having a plurality of interconnected support members. A die pad connected to the support members includes a bottom surface. A downset is connected to the die pad and positioned below the bottom surface. The downset includes at least one wall defining an interior volume. A die is secured to the die pad. At least one wire is electrically connects die to the support members. The interior volume of the downset receives a flow of the mold material to reduce the velocity of the mold material flow around the circuit board.

"In another example, a method of forming a circuit board includes molding a leadframe or leadframe substrate having a plurality of interconnected support members, a die pad connected to the support members and having a bottom surface, and a downset connected to the die pad and positioned below the bottom surface, the downset having at least one wall defining an interior volume. A die is secured to the die pad. The die is electrically connected to the support members with at least one wire. The circuit board is overmolded with an electrically insulating material mold material that flows over the leadframe. The interior volume of the downset receives a flow of the mold material to reduce the velocity of the mold material flow through the downset.

"In another example, a package semiconductor device includes a leadframe or leadframe substrate having a plurality of interconnected support members. A die pad is connected to the support members and has a bottom surface. A downset connected to the die pad is positioned below the bottom surface. The downset has at least one wall defining an interior volume. A die is secured to the die pad. At least one wire electrically connects the die to the support members. Mold material is overmolded around the leadframe, the die, and the at least one wire to electrically insulate the same. The interior volume of the downset receives a flow of the mold material to reduce the velocity of the mold material flow through the downset during overmolding.

"Other objects and advantages and a fuller understanding of the invention will be had from the following detailed description and the accompanying drawings."

For more information, see this patent: Chang, Chia-Yu; Lee, Bob; Su, Steven. Planar Leadframe Substrate Having a Downset below within a Die Area. U.S. Patent Number 9786582, filed January 29, 2016, and published online on October 10, 2017. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=9786582.PN.&OS=PN/9786582RS=PN/9786582

Keywords for this news article include: Electronics, Circuit Board, Texas Instruments Incorporated.

Our reports deliver fact-based news of research and discoveries from around the world. Copyright 2017, NewsRx LLC

(c) 2017 NewsRx LLC, source Business Newsletters

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