By a News Reporter-Staff News Editor at Journal of Engineering -- From Alexandria, Virginia, VerticalNews journalists report that a patent by the inventor Grant, David Alexander (Dallas, TX), filed on May 27, 2015, was published online on August 18, 2015.
The patent's assignee for patent number 9111628 is TEXAS INSTRUMENTS INCORPORATED (Dallas, TX).
News editors obtained the following quote from the background information supplied by the inventors: "This invention is in the field of memory testing. Embodiments of this invention more specifically pertain to the measurement of read margin of read-only memory cells.
"Non-volatile solid-state read/write memory devices are commonplace in many modern electronic systems, particularly in portable electronic devices and systems. Conventional types of non-volatile solid-state memory devices include those referred to as electrically programmable read-only memory (EPROM) devices. Modern EPROM or memory cells include one or more 'floating-gate' transistors that store the data state. In a general sense, these floating-gate transistors are 'programmed' by the application of a bias that enables holes or electrons to tunnel or be injected through a thin dielectric film onto an electrically isolated transistor gate element, which is the floating gate of the transistor. This trapped charge on the floating gate will modulate the apparent threshold voltage of the memory cell transistor, as compared with the threshold voltage with no charge trapped on the floating gate. This difference in threshold voltage can be detected by sensing the resulting difference in source-drain conduction, under normal transistor bias conditions, between the programmed and unprogrammed states. Some EPROM devices are 'erasable' in that the trapped charge can be removed from the floating gate, for example by exposure of the memory cells to ultraviolet light (such memories referred to as 'UV EPROMS') or by application of a particular electrical bias condition that enables tunneling of the charge from the floating gate (such memories referred to as electrically-erasable or electrically-alterable, i.e., EEPROMs and EAPROMS, respectively). 'Flash' memory devices are typically realized by EEPROM memory arrays in which the erase operation is applied simultaneously to a 'block' of memory cells.
"Because of the convenience and efficiency of modern EPROM and EEPROM functions, it is now commonplace to embed non-volatile memory arrays within larger scale integrated circuits, such as modern complex microprocessors, digital signal processors, and other large-scale logic circuitry. Such embedded non-volatile memories can be used as non-volatile program memory storing software routines executable by the processor, and also as non-volatile data storage. On a smaller scale, non-volatile memory cells can realize control registers by way of which a larger scale logic circuit can be configured, or can be used to 'trim' analog levels after electrical measurement.
"As known in the art, 'one-time programmable' ('OTP') memories are also popular, especially in embedded non-volatile memory applications as mentioned above. The memory cells of OTP memories are constructed similarly or identically as UV EPROM cells, and as such are not electrically erasable. But when mounted in an opaque package, without a window through which the memory can be exposed to ultraviolet light, the UV EPROM cells may be programmed one and only one time. In embedded applications, OTP memories are useful for storing the program code to be executed by the embedding microcontroller or microprocessor.
"FIG. 1a illustrates the construction of conventional non-volatile memory cell 5.sub.j,k, which resides in a row j and column k of an EPROM array. In this example, cell 5.sub.j,k includes p-channel metal-oxide semiconductor (MOS) select transistor 2, p-channel MOS floating-gate transistor 4, and n-channel MOS precharge transistor 6, with their source-drain paths connected in series between a high bias voltage Vhi and a low bias voltage Vlo (which may be at ground, for example). The gate of transistor 2 receives word line WL.sub.j* for the row j in which cell 5.sub.j,k resides (and which is a negative logic signal, as indicated by the *), and the gate of transistor 6 receives precharge signal PCHG. The gate of floating-gate transistor 4 is left floating in this example. Sense node SN is at the common drain node of transistors 4 and 6, and is connected to read circuit 8. In this example, read circuit 8 includes a buffer and Schmitt trigger in series, but may alternatively be arranged in any one of a number of known configurations.
"Floating-gate transistor 4 is programmable by the application of a particular bias condition to its source and drain to cause electrons or holes to tunnel or be injected from the source or drain of transistor 4 into its floating gate electrode, and become trapped there. In some instances, the gate of select transistor 2 physically overlies, at least in part, the gate of floating-gate transistor 4 (e.g., in a 'split-gate' arrangement), such that its voltage also plays a role in the programming mechanism. In UV EPROMs (and OTPs), the trapped charge will remain at the floating gate electrode indefinitely subject to leakage, or until photoelectrically recombined. In electrically erasable memories, an erase electrode (not shown in FIG. 1a) to provide the necessary bias for reverse tunneling of the trapped charge. That trapped charge modulates the threshold voltage of transistor 4, typically in a binary sense so that transistor 4 either conducts or does not conduct upon select transistor 2 being turned on. In the particular example of FIG. 1a, p-channel floating gate transistor 4 is considered programmed to a '1' data state if electrons are trapped on its floating gate electrode as a result of the programming operation. In this '1' programmed state, transistor 4 will conduct if it conducts with the application of a negative drain-to-source voltage. Conversely, the '0' data state corresponds to electrons not being trapped on the floating gate electrode of transistor 4, such that transistor 4 does not conduct with the application of a negative drain-to-source voltage.
"In operation, the read cycle for cell 5.sub.j,k begins with precharge signal PCHG being driven active high, which turns on precharge transistor 6; select transistor 2 is held off during this precharge operation, by word line WL.sub.j* being inactive at a logic high level. This operation discharges sense node SN to voltage Vlo, following which precharge signal PCHG is driven inactive low to isolate sense node SN from voltage Vlo. The read of the state of floating-gate transistor 4 is then accomplished by word line WL.sub.j* being driven active to a logic low level, for example in response to a memory address selecting row j in which cell 5.sub.j,k resides. Select transistor 2 is turned on by word line WL.sub.j* driven low, placing a high voltage Vhi (less any voltage drop across transistor 2) at the source of floating-gate transistor 4. If floating-gate transistor 4 has been programmed to its '1' state (i.e., electrons are trapped at its floating gate electrode, reducing the threshold voltage of the device), the negative drain-to-source voltage across transistor 4 will result in source/drain conduction, pulling the voltage at sense node SN high toward voltage Vhi. Conversely, if floating-gate transistor 4 is left in its unprogrammed '0' state (i.e., electrons are not trapped at its floating gate electrode), it will remain nominally non-conductive under the negative drain-to-source voltage, and sense node SN will remain at its discharged low level. In either case, the state of sense node SN will be communicated via read circuit 8 to terminal D_OUT, and communicated externally from the memory in the conventional manner.
"FIG. 1b illustrates the response of voltage V.sub.SN at sense node SN following time t.sub.WL at which word line WL.sub.j* is driven low in the example of FIG. 1a. For the case in which floating-gate transistor 4 is programmed to a '1' state, sense node SN is rapidly pulled high upon select transistor 2 turning on as shown by trace RD(1). For example, the time at which voltage V.sub.SN crosses the trip level V.sub.trip of read circuit 8 may be on the order of 10 nsec in modern OTP memories. Conversely, for floating-gate transistor 4 in its unprogrammed '0' state, sense node SN remains nominally low, and is pulled high only by sub-threshold source/drain leakage, as shown by trace RD(0).
"It has been observed, however, that the leakage characteristics of floating-gate transistors 4 over a population of memory cells 5 will vary from cell to cell (and of course from die to die). Depending on a wide range of manufacturing factors and defects, the sub-threshold leakage of some transistors 4 can be significant. In addition, as well known in the art, floating-gate transistors 4 commonly 'age' in such a manner that source/drain leakage in the unprogrammed state increases over the operating life of the device. An example of the behavior of a weak instance of cell 5.sub.j,k in its unprogrammed state is illustrated in FIG. 1b by trace RD(0).sub.wk. As evident from that trace, voltage V.sub.SN slowly goes high following the energizing of word line WL.sub.j* at time t.sub.WL, due to leakage through transistor 4 in its off state. Voltage V.sub.SN for such a leaky device will eventually reach trip voltage V.sub.trip, causing a false read (i.e., '1' is output by read circuit 8 instead of the correct '0' level). However, the time required for this false data state to be output can be quite long, for example on the order of microseconds (as opposed to the sub-10 nsec timing for a true '1' state). For typical read cycle times, this weak cell 5 may not currently exhibit a read error, but over time, the effects of aging may cause the read error to manifest in later life. In addition, such weaker cells are more vulnerable to read errors caused by noise in the read cycle.
"It is useful for the manufacturer or end user to identify those memories and cells that are weak in this manner, especially considering that these cells will further weaken as they age. However, conventional time-zero electrical testing is not readily able to identify those weakened cells, or to quantify the extent of their weakness. For example, as shown in FIG. 1b, sensing of cell 5.sub.j,k at a reasonable read time t.sub.RD will return the correct '0' state for both the strong '0' case as shown by trace RD(0) and also the weak '0' case as shown by trace RD(0).sub.wk. But the strong and weak cells can be distinguished by the sense node voltage V.sub.SN at read time t.sub.RD. In this example, the difference between difference between sense node voltage V.sub.SN and trip voltage V.sub.trip at a read time t.sub.RD is referred to as the 'read margin'. In the example of FIG. 1b, a weak cell 5.sub.j,k exhibits read margin RM0.sub.--wk, while a strong cell 5.sub.j,k exhibits a much larger read margin RM0.sub.--str.
"Measurement of these read margins would thus give an indication of the distribution of strong and weak cells in the memory array, and would also allow identification of the weaker cells that may limit the reliability and noise tolerance of the memory (enabling replacement of those cells by way of redundancy, for example). While the testing of read margin by way of proxies (e.g., variations in power supply voltages) can lend some indication of read margin, such tests are necessarily indirect and thus prone to both false positives (cells that do not appear weak but in fact are weak) and false negatives (cells that appear weak but in fact are not). Analog measurements of the read margin, for example by directly measuring the analog voltage at sense node SN, but require the costly addition of analog circuitry in the memory architecture.
"While the above discussion pertains to the 'read margin 0' for cells in their unprogrammed '0' state, cells in their programmed '1' state also exhibit a read margin ('read margin 1'). FIG. 1b illustrates the read margin 1 for cell 5.sub.j,k in its '1' state as read margin RM1. Among the population of cells in their '1' state, some will exhibit weaker read margins than others, and are similarly prone to degradation over operating life and eventually failure."
As a supplement to the background information on this patent, VerticalNews correspondents also obtained the inventor's summary information for this patent: "Embodiments of this invention provide circuitry and a method of operating the same for digitally measuring read margin of cells in a non-volatile programmable memory.
"Embodiments of this invention provide such circuitry and corresponding method in which an actual read margin value, rather than simply a pass/fail result, is obtained.
"Embodiments of this invention provide such circuitry and corresponding method that directly measures the read margin, without requiring the implementation of analog circuitry and component matching.
"Embodiments of this invention provide such circuitry in a cost-efficient and area-efficient manner.
"Embodiments of this invention provide such circuitry and corresponding method that readily tests multiple memory cells in parallel, thus reducing test time and test cost.
"Embodiments of this invention provide such circuitry and corresponding method suitable for evaluating individual memory cells as may be useful in failure analysis.
"Embodiments of this invention provide such circuitry and corresponding method that is suitable for measuring read margin for both digital data states.
"Other objects and advantages of embodiments of this invention will be apparent to those of ordinary skill in the art having reference to the following specification together with its drawings.
"Embodiments of this invention may be implemented into the read data path of a non-volatile memory in which the memory cells include a programmable floating-gate transistor in series with a precharge transistor. Read circuitry is coupled to a node between the precharge transistor and the floating-gate transistor in associated cells. A clocked counter counts a number of clock cycles and provides its contents to a latch that is triggered by a transition at the output of memory read circuitry. The latched counter value corresponds to the time at which one or more associated floating-gate memory cells that are programmed to a non-conductive state make a transition, and thus provides a measure of the read margin for the associated cells programmed to that non-conductive state.
"Another aspect of the invention may be implemented in some embodiments in which multiple memory cells are read in parallel. Mask logic masks the outputs of one or more of parallel outputs so that the latch is triggered by selected ones of the parallel cells.
"Another aspect of the invention may be implemented in some embodiments that measure the read margin for cells programmed to a conductive state, such that the output transition is expected to occur within a single clock cycle. An analog circuit, such as a resistor-capacitor network, is coupled to the output of the read circuitry, and the cell of interest is repeatedly read. An analog voltage is read after a number of cycles, that analog voltage corresponding to the duty cycle at the output of the read circuitry, and thus corresponding to the average fraction of the read clock cycle following the transition to the expected output from the cell of interest.
"Other advantages and benefits of embodiments of this invention will be apparent to those skilled in the art having reference to this specification."
For additional information on this patent, see: Grant, David Alexander. Read Margin Measurement in a Read-Only Memory. U.S. Patent Number 9111628, filed May 27, 2015, and published online on August 18, 2015. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=9111628.PN.&OS=PN/9111628RS=PN/9111628
Keywords for this news article include: TEXAS INSTRUMENTS INCORPORATED.
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