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Texas Instruments : Patent Issued for Clock Conditioner Circuitry with Improved Holdover Exit Transient Performance (USPTO 9680484)

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06/22/2017 | 11:30pm CEST

By a News Reporter-Staff News Editor at Journal of Engineering -- From Alexandria, Virginia, VerticalNews journalists report that a patent by the inventors Zhang, Benyong (Auburn, WA); Du, Anjin (Beijing, CN); Shi, Junqiang (Shenzhen, CN), filed on December 2, 2015, was published online on June 13, 2017.

The patent's assignee for patent number 9680484 is TEXAS INSTRUMENTS INCORPORATED (Dallas, TX).

News editors obtained the following quote from the background information supplied by the inventors: "A clock conditioner is typically used to generate desired output clock frequencies with low jitter and low phase noise based on an input reference clock. Typical clock conditioners generate an output clock by phase-locking the output of a voltage controlled oscillator (VCO) or a voltage controlled crystal oscillator (VCXO) to an input reference clock using a phase-locked loop (PLL). The input clock may be a clock signal generated by another component, or it may be a clock that is recovered from a received digital signal.

"In order to improve system-level reliability, two or more clocks signals may be provided as inputs to a clock conditioner. One of these input clocks is selected as the PLL reference clock input. If the selected input clock fails or otherwise becomes unusable, the next available input clock may be selected and used as the new PLL reference clock input. This is commonly referred to as input clock switching. If all available input clocks fail or are otherwise unusable, the clock conditioner must still generate a reasonably accurate output clock for a certain amount of time. In this case, the clock conditioner is said to operate in holdover mode. Different systems may require a clock conditioner to operate in holdover mode for different amounts of time.

"When a clock conditioner is operating in holdover mode and an input clock signal becomes available that is suitable to use as the PLL reference clock input, the clock conditioner exits holdover mode and resumes normal operations mode. This transition from holdover mode to normal operation mode must be completed as quickly and seamlessly as possible. When transitioning from holdover mode to normal operations mode, it is desirable, or required by some systems, to minimize the impact of this transition on the frequency and phase of the output clocks being generated as outputs by the clock conditioner.

"One potential issue that may cause problematic disturbances during the exit-holdover transition is significant phase differences in the counter inputs to the phase detector of a PLL. In a clock conditioner, the inputs to the phase detector of the PLL are an input counter that is driven by a reference clock input and a feedback counter that is driven by a feedback clock generated as an output of the PLL. In the worst case, the phase difference in the inputs to the PLL phase detector can be as large as 180 degrees, since there is no deterministic phase relationship between the outputs to the two counters. Such large phase difference can cause significant disturbances in the operation of PLL, such as delays in the time required for the PLL to relock to the reference clock, delays in completing the exit-holdover transition, and/or transient frequency/phase errors in the output clocks.

"Certain conventional clock conditioners avoid these problems caused by a significant phase difference in the inputs to the phase detector by waiting to exit holdover mode until the phase detector inputs, the input counter and the feedback counter, are phase-aligned. This conventional technique can be used to reduce transient frequency/phase errors in the output clock when exiting holdover. However, one drawback of this conventional technique is that the wait time for the phase detector inputs to align is uncertain and may be too long for certain conditions. For example, if the phase error between the input counter and feedback counter is 180 degrees and the frequency error between these signals is relatively small, the rate of change of the phase difference during the alignment of the two input signals may be very slow. In this case, it may take prohibitively long to wait for the phase alignment of the input counter and the feedback counter inputs to the phase detector. This delay in alignment of the phase detector inputs may prevent the clock conditioner from exiting holdover mode in some cases, as discussed in more detail below. Additionally, the uncertainty in the duration of this alignment delay results in the clock conditioner behaving unpredictably during the holdover transition thus may fail to meet requirements of some systems.

"Accordingly there is a need for an improved clock conditioner capable of quickly and seamlessly exiting holdover mode and further capable of executing the holdover transition in a manner that minimizes problematic disturbances caused by uncertain phase differences in the inputs to the clock conditioner PLL."

As a supplement to the background information on this patent, VerticalNews correspondents also obtained the inventors' summary information for this patent: "According to one aspect of the invention, the disclosure herein includes a timing circuit and associated method comprising: a first divider operable for generating a first input signal based on a feedback signal generated by an oscillator, a second divider operable for generating a second input signal based on a reference clock signal; a PLL operable for generating a control signal for configuring an oscillator to generate a clock signal, wherein the frequency of the clock signal matches the frequency of the second input signal, and wherein the PLL generates the control signal based on the first input signal and the second input signal; and a holdover controller operable for issuing a reset signal to the first divider, wherein the reset signal synchronizes the phase of the first input signal and the second input signal.

"According to another aspect of the invention, the timing circuit further comprises a digital lock detector operable to detect holdover exit conditions based on the first input signal and the second input signal. According to another aspect of the invention, the digital lock detector is further operable to detect holdover exit conditions based on a cycle of frequency comparisons between the first inputs signal and the second input signal. According to another aspect of the invention, the holdover controller is further operable to issue the reset signal concurrent with the initiation of a frequency comparison cycle by the DLD. According to another aspect of the invention, the timing circuit further comprises a flip-flop operable to sample the reset signal. According to another aspect of the invention, the flip-flop is further operable to sample the reset signal synchronously with the second input signal. According to another aspect of the invention, the holdover controller is further operable to initiate a frequency comparison cycle by the DLD based on validation of the reference clock signal. According to another aspect of the invention, the timing circuit further comprises a digital to analog converter operable for generating a holdover control signal, wherein the holdover control signal is generated based on a digital code provided by the holdover controller.

"According to another aspect of the invention, the disclosure herein includes a clock conditioner comprising an oscillator operable for generating a conditioned clock signal based on a control signal and further operable for generating a feedback clock signal, wherein the control signal is generated based on a reference clock signal; and a controller operable for initiating a holdover condition based on a loss of the reference clock signal and further operable to exit a holdover condition by issuing a reset signal that synchronizes the phases of the feedback clock signal with the reference clock signal.

"According to another aspect of the invention, the controller is further operable to signal the replacement of the control signal with a holdover control signal upon initiating a holdover condition. According to another aspect of the invention, the clock conditioner further comprises a digital lock detector (DLD) operable to detect holdover exit conditions based on the feedback clock signal and the reference clock signal. According to another aspect of the invention, the controller is further operable to initiate a frequency comparison cycle by the DLD based on validation of the reference clock signal. According to another aspect of the invention, the controller is further operable to issue the reset signal concurrent with the initiation of a lock detection cycle."

For additional information on this patent, see: Zhang, Benyong; Du, Anjin; Shi, Junqiang. Clock Conditioner Circuitry with Improved Holdover Exit Transient Performance. U.S. Patent Number 9680484, filed December 2, 2015, and published online on June 13, 2017. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=9680484.PN.&OS=PN/9680484RS=PN/9680484

Keywords for this news article include: TEXAS INSTRUMENTS INCORPORATED.

Our reports deliver fact-based news of research and discoveries from around the world. Copyright 2017, NewsRx LLC

(c) 2017 NewsRx LLC, source Science Newsletters

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