By a News Reporter-Staff News Editor at Journal of Engineering -- From Alexandria, Virginia, VerticalNews journalists report that a patent by the inventors Damodaran, Raguram (Plano, TX); Chachad, Abhijeet Ashok (Plano, TX); Bhoria, Naveen (Plano, TX), filed on September 28, 2011, was published online on November 17, 2015.
The patent's assignee for patent number 9189331 is TEXAS INSTRUMENTS INCORPORATED (Dallas, TX).
News editors obtained the following quote from the background information supplied by the inventors: "The following is a description of information regarding cache design. A multi-level cache hierarchy may be inclusion or exclusion. In an inclusive cache hierarchy data stored at lower levels of the cache are present at all higher levels of the cache hierarchy. In an exclusive cache hierarchy data can only be stored at one level of the hierarchy. In a non-exclusive cache hierarchy is neither strictly inclusive nor strictly exclusive. Thus data stored at lower levels of the cache may be stored at higher levels of the cache but need not be.
"When a write access occurs to an address stored in a lower level cache, the data in that cache is modified and the status bits for that cache line are updated to reflect the fact that the data has been modified. This is called the line is dirty. This concept is only relevant to a cache that implements a write-back policy. There are two primary cache writing policies called write-back and write-through.
"Most cache implementations utilize a write-back policy. Under a write-back policy, when a write access occurs to a given address the write takes place in the lowest level of the cache hierarchy that can service the write. Higher level caches are not modified. If the data is stored in multiple levels of the hierarchy, the data at the lowest level of the hierarchy that actually serviced the write access becomes the current data for that address. The data at the higher levels of the hierarchy becomes stale because it holds the old value. Under the write-back policy, when a cache at a lower level of the hierarchy evicts a data line that is dirty, the data of the dirty line is written back to higher levels of the hierarchy. There are two problems associated with a write-back cache hierarchy: coherence and delayed updates.
"The write-back cache coherence problem is a follows. For inclusive and non-exclusive caches, the same data line can be present at multiple levels of the hierarchy. When a write access to the lowest level of the hierarchy makes a cache line dirty, the data at higher levels becomes outdated. This is a problem if the higher levels of the hierarchy can be accessed directly without first accessing the lower levels of the hierarchy. This problem also exists in a more generalized model, where the highest level of the cache hierarchy is RAM storage rather than a cache. If the cached data at a lower level of the hierarchy has a dirty copy of the data in the RAM, and the system allows direct access to the RAM, the most up-to-date data must be returned. If this is not done the memory consistency guarantees for the system is violated. If the memory system provides a coherency guarantee, then the various levels of the cache hierarchy must remain coherent with each other. Thus each level of the cache hierarchy must have visibility into the other levels of the hierarchy in order to always have access to the most up-to-date version of the data.
"The write-back cache delayed update problem is a follows. According to the write-back cache policy writes are not reflected to higher levels of the cache hierarchy until the lowest level cache line that contains modified data is evicted. At that time the next level is updated and marked dirty. The update then stops until the line at this level of the hierarchy is evicted and written back, and so on. In a system that provides no coherency guarantee for this data, independent accesses to the higher levels of the hierarchy will continue to sample stale data for an indefinite amount of time until the updates propagate through to the higher levels of the hierarchy.
"A less common cache policy is known as write-through. Under this policy when a write occurs to a given address, the lowest level of the cache hierarchy that can service the write access will both service the write and forward the write to the next level of the hierarchy. The next level will also service the write and forward it. Each level of the hierarchy will do likewise. In a write-through hierarchy, a write that hits a line in the cache does not need to mark the line dirty, because the write data will be forwarded to all levels of the hierarchy. Thus all levels of the hierarchy will remain current with respect to the data that was written.
"The main problem with a write-through cache is the increased memory traffic associated with forwarding all write accesses throughout the hierarchy. Whereas a write-back cache can act as a filter between levels of the hierarchy, a write-through cache does not filter writes."
As a supplement to the background information on this patent, VerticalNews correspondents also obtained the inventors' summary information for this patent: "This invention is a cache system with a memory attribute register having plural entries. Each entry stores a write-through or a write-back indication for a corresponding memory address range. On a write to cached data the cache the cache consults the memory attribute register for the corresponding address range. Writes to addresses in regions marked as write-through always update all levels of the memory hierarchy. Writes to addresses in regions marked as write-back update only the first cache level that can service the write. The memory attribute register is preferably a memory mapped control register writable by the central processing unit.
"The write enable bit of each entry of said memory attribute register is located in a first level cache. This indication is communicated to other levels of memory hierarchy.
"A second level memory includes cache and directly addressable local memory. The entry of the memory attribute register for addresses in the local memory is fixed as write-back."
For additional information on this patent, see: Damodaran, Raguram; Chachad, Abhijeet Ashok; Bhoria, Naveen. Programmable Address-Based Write-Through Cache Control. U.S. Patent Number 9189331, filed September 28, 2011, and published online on November 17, 2015. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=9189331.PN.&OS=PN/9189331RS=PN/9189331
Keywords for this news article include: TEXAS INSTRUMENTS INCORPORATED.
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