By a News Reporter-Staff News Editor at Politics & Government Week -- A patent application by the inventors CHEN, MIN (SAN DIEGO, CA); REDDY, VIJAY KUMAR (PLANO, TX), filed on January 16, 2014, was made available online on July 24, 2014, according to news reporting originating from Washington, D.C., by VerticalNews correspondents.
This patent application is assigned to Texas Instruments Incorporated.
The following quote was obtained by the news editors from the background information supplied by the inventors: "An integrated circuit (IC or chip) generally comprises a plurality of circuit paths. A 'circuit path' may be interpreted to mean arrangements of electronic circuitry components through which electrical current may flow when biased. Each path generally comprises a plurality of transistors and other elements such as resistors and capacitors, along with parasitics. In some cases, each path may be designed to perform a specific function. One of these paths may be the most poorly-performing (i.e., slowest) path, due to any of a variety of reasons, such as circuit complexity. The circuit path that limits the overall performance frequency of other circuit paths and/or the load itself may be termed herein the 'critical path.'
"Any of a variety of factors, such as temperature, voltage, manufacturing variation and other factors not specifically disclosed herein may affect the speed of the critical path, as well as that of any of the other circuit paths. For example, because the voltage supplied to a circuit path is applied to some or all of the transistors in the circuit path, the voltage dictates, at least in part, the performance of the transistors in the path. In turn, the performance of the transistors dictates, at least in part, the speed of the circuit path itself. Thus, if a voltage that is delivered to a circuit path is undesirably high or low (i.e., the voltage has been substantially altered by various circuit components and phenomena between a voltage source and the circuit path), the performance speed of the circuit path may likewise be undesirably high or low.
"In some cases, such factors may impact the speed of the critical path and/or another path such that the speed of the path may become excessively low or excessively high. If the speed becomes excessively low, the path and/or the load may cease to function. Conversely, if the speed becomes excessively high, the chip and/or the load may waste power or even become damaged.
"A system on a chip or system on chip (SoC or SOC, hereafter SOC) is an IC which integrates all components of a computer or other electronic system into a single chip/die. The SOC generally includes digital, analog, mixed-signal, and often radio-frequency circuitry and functions, all on a single chip.
"On-chip sensors (OCS) are known to implement techniques such as adaptive voltage scaling (AVS) and dynamic voltage/frequency scaling (DVFS) to dynamically optimize the power and performance of a SOC by monitoring the OCS output under the process variation(s). On the other hand, the SOC also relies on the OCS to create an aging (over time) guardband for reliability purposes. To ensure a safe guardband, the OCS is designed to perform as a bounding device as it ages. To perform properly, the OCS should drift more than the most sensitive logic structure on the chip, and thus require more compensation (typically more VDD) than other circuits to resume its time zero performance.
"Conventional OCSs can be based on ring oscillators (ROs). The RO frequency is measured as an indicator of the circuit's performance. Due to the close-loop nature of a RO, the RO's sensitivity to aging is limited due to the averaging effect of its delay drift. Although the sensitivity of the RO can be improved through transistor upsizing and increased transistor gate stacking, this improvement results in the loss of otherwise usable die size.
"One example RO-based OCS is the NOR3 and/or NAND3 version of the SMARTREFLEX.TM. sensor from Texas Instruments Incorporated. As known in the art, an odd number of logic stages with feedback from the output to the input enables oscillation. Load capacitors (C.sub.L) to ground are generally added (typically 10 fF to 100 fF) to adjust the oscillation frequency. Such OCS are disclosed along with related circuitry and methods for utilizing in U.S. Pat. Nos. 7,307,471 and 7,793,119 both to Gammie et al. and assigned to Texas Instruments Incorporated (hereafter Gammie '471 and Gammie '119), the same assignee as the assignee of this patent application. The subject matter in Gammie '471 and Gammie '119 are both incorporated by reference into this patent application."
In addition to the background information obtained for this patent application, VerticalNews journalists also obtained the inventors' summary information for this patent application: "Disclosed embodiments describe a variability and aging compensating on-chip sensor (OCS) related to the SMARTREFLEX.TM. ring oscillators (RO)-based sensors provided by Texas Instruments Incorporated, modified to have a gate structure including at least one disclosed discharge or charge path that can be active during charging or discharging. As used herein, a disclosed OCS may be on the IC itself, or in the scribe line of a substrate (e.g., a wafer) having a plurality of ICs.
"At least one NOR PMOS stack is for disclosed OCS including NOR gates and/or at least one NAND NMOS stack is for disclosed OCS including NAND gates. Disclosed discharge and charging paths have been found to further increase the delay contribution from the transistor stack leading to a higher V.sub.DD sensitivity for a given aging induced .DELTA.Vt, and the discharge/charge path leads to more current needed, resulting in a lower effective Vt leading to a lower sensitivity to .DELTA.VDD. Higher Vt sensitivity with lower VDD sensitivity is recognized herein to be helpful when a larger (safer) guardband is needed. For example, drawing more current compared to the NOR3 gate in the known SMARTREFLEX.TM. OCS 100 shown in FIG. 1B described below, not only is recognized to increase the sensor's frequency response to PMOS device aging, but also reduces the sensor's undesirable ability to restore its performance with VDD compensation.
"The combination of these factors enables a higher (larger) OCS guardband, which can have a strong dependency on the effectiveness of the pull down path for OCS including NOR and/or pull up path for OCS including NAND. For example, by tuning the size of the PMOS device(s) in the disclosed pull down path for OCS NOR or the size of the NMOS device(s) in the disclosed pull up path for OCS NAND, the sensitivity of the OCS can be designed to be set to a desired value. Through an optional second serial connected PMOS for NOR-based OCS or serial connected NMOS for NAND-based OCS in the disclosed discharge/charge path, the PMOS pull down path for OCS NOR and/or the NMOS pull up path for OCS NAND can also be shut off. In this case, a lower relative guardband provided by the OCS is similar to the guardband provided by SMARTREFLEX.TM. sensors disclosed by Gammie '471 and Gammie '119, which can be switchably provided by disclosed OCS having this feature using a suitable enable signal. This switching feature may be desirable because as noted above, switching off the discharge/charge path results in the standard device and thus the current (i.e., power) dissipation will be a little bit lower if that is a user' consideration. Also, it may also be the case that after going through the flow in FIG. 3B described below, that the bounding guardband provided by the standard configuration is sufficient.
"Compared with the known SMARTREFLEX.TM. sensors described above, disclosed OCSs uniquely have 1) for OCS including NOR an extra PMOS pull down discharge path including at least one PMOS device inserted between the NOR gate PMOS stack, making it more sensitive to PMOS degradation under negative-bias temperature instability (NBTI), 2) and/or for OCS including NAND an extra NMOS pull up charging path inserted between the NAND gate NMOS stack, making it more sensitive to NMOS degradation under positive-bias temperature instability (PBTI), and optionally 3) a serial connected PMOS (for NOR-based OCS) /NMOS (for OCS NAND) to control the on/off of the disclosed pull down or pull up discharge/charge path.
BRIEF DESCRIPTION OF THE DRAWINGS
"Reference will now be made to the accompanying drawings, which are not necessarily drawn to scale, wherein:
"FIG. 1A illustrates an example OCS comprising a first NAND-based ring oscillator and a second NOR-based ring oscillator that include logic elements having disclosed discharge and charge paths, respectively, that can be used with an adaptive voltage scaling system (AVS), according to an example embodiment.
"FIG. 1B is a transistor level schematic of the NOR gate coupled to the inverter encircled in FIG. 1A for a known circuit arrangement.
"FIG. 2A is a transistor level sub-circuit schematic of a portion of a disclosed OCS being a NOR gate coupled to an inverter that further includes a disclosed discharge path comprising a single pull down PMOS transistor operable during the charging of the NOR3 PMOS stack, according to an example embodiment.
"FIG. 2B is a transistor level sub-circuit schematic of a portion of an OCS being a NOR gate coupled to an inverter that includes a disclosed discharge path comprising a first pull down PMOS transistor in series with a second pull down PMOS transistor with enable input operable during the charging of the NOR3 PMOS stack when enabled, according to an example embodiment.
"FIG. 2C is a transistor level sub-circuit schematic of a portion of an OCS being a NAND3 gate coupled to an inverter that includes a disclosed charging path comprising a pair of series connected NMOS transistors one having an enable input operable during discharging of the NAND3 NMOS stack when enabled, according to an example embodiment. This circuit is the complement of the portion of an OCS shown in FIG. 2B.
"FIG. 3A demonstrates use of a disclosed OCS with disclosed discharge path that can be used in a Device Parametric Shift Evaluation (DPSE) flow, shown including a SoC providing a digital bank that controls enable inputs to gates of the enable PMOS transistors in the respective PMOS transistor series pull downs in the discharge paths, according to an example embodiment.
"FIG. 3B is a flow chart showing steps for an example adaptive guardband tuning, according to an example embodiment.
"FIG. 4 is a depiction of a SOC chip with a disclosed OCS on the chip having the SOC in an exploded view shown providing an efuse arrangement for setting a frequency target, a supply voltage regulator and a body voltage generator for both PMOS devices and NMOS devices, according to an example embodiment.
"FIG. 5. is a cross-sectional view of a portion of a logic circuit (e.g., a complementary metal oxide semiconductor, or CMOS circuit) comprising an NMOS transistor and a PMOS transistor that can be used in disclosed ICs and OCS having gate stacks including a metal gate on a high-k dielectric.
"FIGS. 6A and 6B show .DELTA.V.sub.DD vs. .DELTA.V.sub.t data including data from some example balanced and unbalanced critical paths, a control OCS, and a disclosed OCS evidencing only disclosed OCS can provide the proper (i.e. highest V.sub.DD) bounding V.sub.DD guardband (GB), with the GB shown provided by the disclosed OCS being large enough to be safe GBs to guard balanced and unbalanced paths for both NBTI and PBTI."
URL and more information on this patent application, see: CHEN, MIN; REDDY, VIJAY KUMAR. Variability and Aging Sensor for Integrated Circuits. Filed January 16, 2014 and posted July 24, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=3983&p=80&f=G&l=50&d=PG01&S1=20140717.PD.&OS=PD/20140717&RS=PD/20140717
Keywords for this news article include: Texas Instruments Incorporated.
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