"Thin Film Transistor Array Formed Substrate, Image Display Device Substrate and Manufacturing Method of Thin Film Transistor Array Formed Substrate" in Patent Application Approval Process (USPTO 20180061892)
By a News Reporter-Staff News Editor at Electronics Newsweekly -- A patent application by the inventors CHUJO, Hina (Taito-ku, JP); Ishizaki, Mamoru (Taito-ku, JP), filed on October 23, 2017, was made available online on March 8, 2018, according to news reporting originating from Washington, D.C., by VerticalNews correspondents.
This patent application is assigned to Toppan Printing Co. Ltd.
The following quote was obtained by the news editors from the background information supplied by the inventors: "Field of the Invention
"The present invention relates to a substrate for forming a thin film transistor array, an image display device substrate and a manufacturing method of a substrate for forming a thin film transistor array.
"Discussion of the Background
"To form patterns of a semiconductor layer and a protection layer in the thin film transistors, a method is utilized in which each of the semiconductor layer and the protection layer are formed on the entire surface, resist patterns are formed, and etching is applied to the resist patterns using etchant so as to form the patterns. However, with this method, the resist has to be film-formed followed by the etching for every time when forming respective patterns. As a result, the number of manufacturing steps increases.
"As an example, according to WO2012/172985, thickness of the resist is adjusted to form the pattern by using only one photolithography process. However, the photolithography process cannot be omitted.
"On the other hand, when using a printing technique to form the semiconductor layer and the protection layer, especially when liquid is used for the material of the semiconductor layer and the protection layer, desired pattern may not be formed.
"FIGS. 6A and 6B are plan views schematically showing an example of a conventional thin film transistor array formed substrate 50, and FIG. 6C shows a cross-sectional view sectioned across A-A' line of FIG. 6B.
"As shown in FIG. 6A, when viewing a layout as a planar arrangement, the gate electrode 2 is connected to the gate wiring 2', the source wiring 4 also serves as the source electrode, the source wiring 4 has periodic notch portions, the source wiring 4 intersects the gate wiring 2', and the notch portions of the source wiring 4 are formed on the gate electrode 2. Drain electrodes 5 are formed in the notch portions of the source wiring 4, facing the source wiring 4.
"In the case where the semiconductor layer 6 is formed on the thin film transistor array formed substrate 50 which is formed in this manner, and the protection layer 7 is formed in a stripe pattern, as shown in FIG. 6B, the semiconductor layer 6 can be formed to connect the source wiring 4 and the drain electrode 5, however, the protection layer 7 may be formed to cover a part of the semiconductor layer 6, the source wiring 4 and the gate insulation layer 3, excluding a part of semiconductor layer 6 in the drain electrode 5 side and a part of the source wiring 4. In other words, a part of the semiconductor layer 6 may not be covered by the protection layer 7.
"As shown in FIG. 6C, where the cross-sectional view across the line A-A' shown in FIG. 6B is illustrated, the gate electrode 2 and the gate wiring 2' are formed on the substrate 1, which are covered by the gate insulation layer 3, and further the source wiring 4 and the drain electrode 5 are formed thereon. The semiconductor layer 6 is formed at a channel portion between the source wiring 4 and the drain electrode 5, and the protection layer 7 is formed to cover the source wiring 4 and the semiconductor layer 6, excluding a part of the semiconductor layer 6 on the drain electrode 5 side.
"Thus, according to the conventional structure, the shape of the protection layer 7 is sometimes worsened. The inventors have found out the cause of this problem is that liquid state ink on the wiring flows onto the gate insulation layer 3.
"In FIG. 6A, the surface of the gate insulation layer 3 has ink affinity properties, and the surfaces of the source wiring 4, the drain electrode 5 and the pixel electrode 9 have ink repellent properties. Since the ink used for printing the semiconductor layer 6 is liquid, but has properties being unlikely to be influenced by the wettability of the surface to be printed, the semiconductor layer 6 can be printed in a stripe shape as expected. On the other hand, an ink used for printing the protection layer 7 is also a liquid. However, an ink affinity portion of the surface to be printed is likely to be wet and an ink repellent portion is unlikely to be wet, whereby the ink on the source wiring 4 and the drain electrode 5 is repelled to move onto the gate insulation layer 3, producing an irregular shape shown in FIGS. 6B and 6C. This is what the inventors have discovered."
In addition to the background information obtained for this patent application, VerticalNews journalists also obtained the inventors' summary information for this patent application: "According to an aspect of the present invention, a thin film transistor array formed substrate includes a gate electrode, a gate insulation layer, a source wiring structure including a source wiring and a source electrode, a drain electrode, a pixel electrode connected to the drain electrode, a semiconductor layer forming in a stripe shape having a longitudinal side extending in a direction that the source wiring extends, and a protection layer formed to cover an entire portion of the semiconductor layer. The source wiring structure has notch portions positioned in the direction that the source wiring extends such that the notch portions overlap with the gate electrode, the source wiring has a first portion having a first width where the notch portions are formed and a second portion having a second width larger than the first width where no notch portions are formed, and the source wiring has an opening in the second portion."
URL and more information on this patent application, see: CHUJO, Hina; Ishizaki, Mamoru. Thin Film Transistor Array Formed Substrate, Image Display Device Substrate and Manufacturing Method of Thin Film Transistor Array Formed Substrate. Filed October 23, 2017 and posted March 8, 2018. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PG01&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.html&r=1&f=G&l=50&s1=%2220180061892%22.PGNR.&OS=DN/20180061892&RS=DN/20180061892
Keywords for this news article include: Business, Electronics, Semiconductor, Photolithography, Toppan Printing Co. Ltd.
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