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Business Machines : Patent Issued for Selective Dielectric Spacer Deposition for Exposing Sidewalls of a finFET (USPTO 9111962)

08/27/2015 | 03:24pm US/Eastern

By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Alexandria, Virginia, VerticalNews journalists report that a patent by the inventors Alptekin, Emre (Wappingers Falls, NY); Jain, Sameer H. (Beacon, NY); Sardesai, Viraj Y. (Poughkeepsie, NY); Tran, Cung D. (Newburgh, NY); Vega, Reinaldo A. (Wappingers Falls, NY), filed on March 20, 2014, was published online on August 18, 2015.

The patent's assignee for patent number 9111962 is INTERNATIONAL BUSINESS MACHINES CORPORATION (Armonk, NY).

News editors obtained the following quote from the background information supplied by the inventors: "The present disclosure relates to a semiconductor structure, and particularly to a method of forming a sidewall spacer for a fin field effect transistor (finFET) selectively on sidewalls of a gate electrode, and structures formed by the same.

"A conventional gate spacer formation process includes conformal deposition of a dielectric material layer and a subsequent anisotropic etch that removes horizontal portions of the deposited dielectric material layer. In the case of a fin field effect transistor, therefore, vertical portions of the deposited dielectric material layer are present on the sidewalls of semiconductor fins. In order to remove the vertical portions of the deposited dielectric material layer from the sidewalls of the semiconductor fins, an extended anisotropic etch process must be employed. Collateral etching of other dielectric materials, such as a shallow trench isolation structure, must be minimized during the extended anisotropic etch process for removing the vertical portions of the deposited dielectric material layer from the sidewalls of the semiconductor fins. The need to remove the deposited dielectric material from the sidewalls of the semiconductor fins imposes severe limitations on selection of dielectric materials that can be employed for the conventional gate spacer."

As a supplement to the background information on this patent, VerticalNews correspondents also obtained the inventors' summary information for this patent: "Angled directional ion beams are directed to sidewalls of a gate structure that straddles at least one semiconductor fin. The directions of the angled directional ion beams are contained within a vertical plane that is parallel to the sidewalls of the at least one semiconductor. A pair of gate spacers are formed on sidewalls of the gate structure by accumulation of the deposited dielectric material from the angled directional ion beams and without use of an anisotropic etch, while the sidewalls of the semiconductor fins parallel to the directional ion beams remain physically exposed. A selective epitaxy process can be performed to form raised active regions by growing a semiconductor material from the sidewalls of the semiconductor fins.

"According to an aspect of the present disclosure, a method of forming a semiconductor structure is provided. A semiconductor fin extending along a lengthwise direction is formed on a substrate. A gate structure is formed over, and across, the semiconductor fin. A dielectric material liner is formed on surfaces of the semiconductor fin and the gate structure employing a pair of directional ion beam deposition processes. A directional ion beam contained within a vertical plane defined by the lengthwise direction and a vertical direction impinges on the surfaces of the semiconductor fin and the gate structure during each of the pair of directional ion beam deposition processes.

"According to another aspect of the present disclosure, a semiconductor structure includes a semiconductor fin that is located on a substrate and extending along a lengthwise direction, a gate structure straddling the semiconductor fin and including a stack of a gate dielectric and a gate electrode, and a dielectric material liner located on the semiconductor fin. Portions of the dielectric material liner in contact with a top surface of the semiconductor fin and an end wall of the semiconductor fin have a same width as the semiconductor fin."

For additional information on this patent, see: Alptekin, Emre; Jain, Sameer H.; Sardesai, Viraj Y.; Tran, Cung D.; Vega, Reinaldo A.. Selective Dielectric Spacer Deposition for Exposing Sidewalls of a finFET. U.S. Patent Number 9111962, filed March 20, 2014, and published online on August 18, 2015. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=9111962.PN.&OS=PN/9111962RS=PN/9111962

Keywords for this news article include: Electronics, Semiconductor, INTERNATIONAL BUSINESS MACHINES CORPORATION.

Our reports deliver fact-based news of research and discoveries from around the world. Copyright 2015, NewsRx LLC

(c) 2015 NewsRx LLC, source Technology Newsletters

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