By a News Reporter-Staff News Editor at Journal of Engineering -- Cadence Design Systems, Inc. (San Jose, CA) has been issued patent number 9104830, according to news reporting originating out of Alexandria, Virginia, by VerticalNews editors.
The patent's inventors are Salowe, Jeffrey (Los Gatos, CA); Raj, Satish (Saratoga, CA).
This patent was filed on June 28, 2013 and was published online on August 11, 2015.
From the background information supplied by the inventors, news correspondents obtained the following quote: "Integrated circuits, or ICs, are created by patterning a substrate and materials deposited on the substrate. The substrate is typically a semiconductor wafer. The patterned features make up devices and interconnections. This process generally starts with a designer creating an integrated circuit by hierarchically defining functional components of the circuit using a hardware description language. From this high-level functional description, a physical circuit implementation dataset is created, which is usually in the form of a netlist. This netlist identifies logic cell instances from a cell library, and describes cell-to-cell connectivity.
"Many phases of these electronic design activities may be performed with computer aided design (CAD) tools or electronic design automation (EDA) systems. For example, an integrated circuit designer may use a set of layout EDA application programs, such as a layout editor, to create a physical integrated circuit design layout from a logical circuit design. The layout EDA application uses geometric shapes of different materials to create the various electrical components on an integrated circuit and to represent electronic and circuit IC components as geometric objects with varying shapes and sizes. After an integrated circuit designer has created an initial integrated circuit layout, the integrated circuit designer then verifies and optimizes the integrated circuit layout using a set of EDA testing and analysis tools. Verification may include, for example, design rule checking to verify compliance with rules established for various IC parameters. The EDA layout editing tools are often performed interactively so that the designer can review and provide careful control over the details of the electronic design.
"Typically, geometric information about the placement of the nodes and components onto the chip is determined by a placement process and a routing process. The placement process is a process for placing electronic components or circuit blocks on the chip and the routing process is the process for creating interconnections between the blocks and components according to the specified netlist. The task of all routers is the same--routers are given some pre-existing polygons consisting of pins on cells and optionally some pre-routes from the placers to create geometries so that all pins assigned to different nets are connected by wires and vias, that all wires and vias assigned to different nets do not overlap, and that all design rules are obeyed. That is, a router fails when two pins on the same net that should be connected are open, when two pins on two different nets that should remain open are shorted, or when some design rules are violated during routing.
"A layout file is created from the placement and routing process, which assigns logic cells to physical locations in the device layout and routes their interconnections. The physical layout is typically described as many patterned layers, and the pattern of each layer is described by the union of a set of polygons. The layout data set is stored, for example in GDSII ('Graphic Data System II') or OASIS ('Open Artwork System Interchange Standard') formats. Component devices and interconnections of the integrated circuit are constructed layer by layer. A layer is deposited on the wafer and then it is patterned using a photolithography process and an etch process.
"Traditionally, layout track pattern is consist of parallel tracks with uniform pitches, and the tracks cover entire coordinate space. This conventional approach does not satisfy the needs for electronic layout with a typical half-pitch of 14 nm or below. With the typical half-pitch advancing to 14 nm or below, the track patterns for a certain metal layer may be required or desired to be region based where one track pattern may be associated with or assigned to a region on one layer, while another track pattern may be associated with or assigned to another region on the same layer. Some designs may even demand or desire non-uniform track patterns. Conventional approaches do not allow periodic changes of track pitches and definitions of regions where one or more track patterns are active. These track pattern requirements pose a challenge for physical design implementation, especially for interactive layout editing. In addition, users may need to interactively define track pattern(s) during the chip floorplanning or placement stage and follow such track pattern(s) during subsequent physical design stages such as routing, post-layout optimization, engineering change order (ECO), or even specific physical design tasks such as wire editing.
"In addition, advanced manufacturing groups have new requirements on where wires or interconnects may be routed. In particular, some routing tracks are intended for double-width wires, some are intended for single-width wires, and so on. Routing tracks, as they were originally devised, applied to every net or connection in the design. To address this, the user must explicitly add the constraints of the track patterns to the routing rules, which is impractical and prone to errors. Moreover, there has been no way to address trackPattern constraints on automatically-generated rules. Some advanced technologies have complex grid requirements. One such requirement is to restrict routing grids in a particular area. Another approach is to give several possible sets of grids, and then to assign one to a given area. The current track pattern representation applies to an entire layer. There is no representation that limits the bounds of a track pattern. Nor is there a representation that maps track patterns to a particular area
"Thus, there exists a need for methods, systems, and articles of manufacture for assigning track patterns to regions of an electronic design."
Supplementing the background information on this patent, VerticalNews reporters also obtained the inventors' summary information for this patent: "Disclosed are method(s), system(s), and article(s) of manufacture for assigning track patterns to regions of an electronic design in one or more embodiments. One aspect is directed at tessellating an area on a layer of an electronic design subject to one or more track pattern requirements, and dynamically maintaining the tessellation structure obtained or derived from the tessellation during early stages of the implementation of the electronic design such as floorplanning, placement, or routing. The tessellation pattern or the tessellation structure is constructed by taking the track patterns or track pattern groups into consideration and thus may be used to guide the implementation of the electronic design, while complying with the requirements explicitly specified or implicitly derived from the track patterns or track pattern groups. Another aspect is directed at identifying or creating multiple sub-areas for an area on a layer of an electronic design, and assigning or associating a track pattern or a track pattern group to each of the sub-areas, instead of applying a track pattern or a track pattern group to the entire layer.
"Various embodiments ensure that electronic designs are implemented during early stages of the design process (e.g., floorplanning, placement, or routing) to comply with not only the various design rules but also the additional track pattern requirements. Some embodiments ensure that electronic designs are implemented during early stages of the design process in a correct-by-construction manner to comply with not only the various design rules but also the additional track pattern requirements while the electronic design is being implemented and prior to the performance of any design rule check (DRC) process or post-route optimization processes.
"Some embodiments are directed at a hardware system that may be invoked to perform any of the methods, processes, or sub-processes disclosed herein. The hardware system may include at least one processor or at least one processor core, which executes one or more threads of execution to perform any of the methods, processes, or sub-processes disclosed herein in some embodiments. The hardware system may further include one or more forms of non-transitory machine-readable storage media or devices to temporarily or persistently store various types of data or information. Some exemplary modules or components of the hardware system may be found in the System Architecture Overview section below.
"Some embodiments are directed at an article of manufacture that includes a non-transitory machine-accessible storage medium having stored thereupon a sequence of instructions which, when executed by at least one processor or at least one processor core, causes the at least one processor or the at least one processor core to perform any of the methods, processes, or sub-processes disclosed herein. Some exemplary forms of the non-transitory machine-readable storage media may also be found in the System Architecture Overview section below."
For the URL and additional information on this patent, see: Salowe, Jeffrey; Raj, Satish. Methods, Systems, and Articles of Manufacture for Assigning Track Patterns to Regions of an Electronic Design. U.S. Patent Number 9104830, filed June 28, 2013, and published online on August 11, 2015. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=9104830.PN.&OS=PN/9104830RS=PN/9104830
Keywords for this news article include: Cadence Design Systems Inc.
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