By a News Reporter-Staff News Editor at Journal of Engineering -- Mentor Graphics Corporation (Wilsonville, OR) has been issued patent number 9087167, according to news reporting originating out of Alexandria, Virginia, by VerticalNews editors.
The patent's inventor is Veerse, Fabrice Alain Robert (La Rochette, FR).
This patent was filed on July 11, 2012 and was published online on July 21, 2015.
From the background information supplied by the inventors, news correspondents obtained the following quote: "Device parameters of two identically designed devices in an integrated circuit may show a variation after fabrication. The variation is called device mismatch. For transistors, device mismatch may include variations of device parameters such as gate length and width, gate oxide thickness, threshold voltage, and doping levels. Device mismatch can have a significant impact on circuit performance such as speed, accuracy and power consumption. A recent statistical analysis of experimental data revealed that a 30% variation (3.sigma.) of transistors' drive-current within a chip causes an equal variation in the circuit signal propagation delay. With the continuing scaling of semiconductor processes, the problems of circuit performance variations due to device mismatch are becoming more pronounced. Furthermore, these problems can be amplified by the low-power and low-voltage operation preferred in commercial electronic products.
"It is thus important for circuit designers to be able to predict circuit performance variations due to device mismatch. A conventional way of estimating the statistical distribution of circuit performance (mismatch analysis) is the Monte Carlo analysis. In the Monte Carlo analysis, device mismatch is modeled as a set of randomly generated samples that represent the probability distributions of device parameters. The circuit is then repetitively simulated with the random device samples and the statistics of the resulting performance are collected. One major drawback of this approach is the large number of circuit simulations needed. This number can be over hundreds to thousands. Another conventional way of the mismatch analysis, the worst case analysis, also suffers from the same problem. The number of simulations required by the worst case analysis is largely dependent on the number of device parameters. A recent study reported the number of the required simulations can exceed eight hundred.
"For practical applications, methods of mismatch analysis that do not require repeated circuit simulations are highly desirable."
Supplementing the background information on this patent, VerticalNews reporters also obtained the inventor's summary information for this patent: "Aspects of the invention relate to techniques for predicting circuit performance variations due to device mismatch. According to various implementations of the invention, circuit simulation is performed to generate circuit simulation results based on a circuit description of a circuit design that comprises circuit elements and information of circuit element parameters. The circuit description may be in the form of a transistor-level netlist. The information of circuit element parameters may comprise nominal circuit element parameter values, which may be computed based on a statistics model for circuit element parameter variations. The circuit simulation may employ a harmonic balance method.
"Based on the simulation results, sensitivity information for the circuit design may be computed. The sensitivity information may comprise adjoint sensitivity information. The adjoint sensitivity information may be obtained by solving an adjoint system involving a harmonic-balance Jacobian matrix.
"Also based on the simulation results, current/charge deviations caused by individual circuit element parameter variations may be computed. The simulation results may comprise nominal current/charge values for the circuit elements. Accordingly, the current/charge deviations are computed with respect to the nominal current/charge values.
"Based on the sensitivity information and the current/charge deviations, steady-state mismatch effect information is determined. The determination may comprise first computing output parameter deviations caused by the individual variations of the circuit element parameters based on the sensitivity information and the current/charge deviation and then computing a total output parameter deviation based on the output parameter deviations. The total output parameter deviation computation may comprise calculating square root of the sum of the squares of the output parameter deviations."
For the URL and additional information on this patent, see: Veerse, Fabrice Alain Robert. Prediction of Circuit Performance Variations Due to Device Mismatch. U.S. Patent Number 9087167, filed July 11, 2012, and published online on July 21, 2015. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=9087167.PN.&OS=PN/9087167RS=PN/9087167
Keywords for this news article include: Mentor Graphics Corporation.
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