Renesas Electronics Corporation announced that it has developed circuit technologies for an embedded spin-transfer torque magnetoresistive random-access memory (STT-MRAM, hereinafter MRAM) test chip with fast read and write operations. Fabricated using a 22-nm process, the microcontroller unit (MCU) test chip includes a 10.8-megabit (Mbit) embedded MRAM memory cell array. It achieves a random read access frequency of over 200 MHz and a write throughput of 10.4-megabytes-per-second (MB/s).

As IoT and AI technologies continue to advance, MCUs used in endpoint devices are expected to deliver higher performance than ever. The CPU clock frequencies of high performance MCUs are in the hundreds of MHz, so to achieve greater performance, read speeds of embedded non-volatile memory need to be increased to minimize the gap between them and CPU clock frequencies. MRAM has a smaller read margin than the flash memory used in conventional MCUs, making high speed read operation more difficult.

On the other hand, for write performance, MRAM is faster than flash memory because it requires no erase operation before performing write operations. However, shortening write times is desirable not only for everyday use, but also for cost reduction of writing test patterns in test processes and writing control codes by end product manufacturers. MRAM reading is generally performed by a differential amplifier (sense amplifier) to determine which of the memory cell current or the reference current is larger.

However, because the difference in memory cell currents between the 0 and 1 states (the read window) is smaller for MRAM than for flash memory, the reference current must be precisely positioned in the center of the read window for faster reading. The newly developed technology introduces two mechanisms. The first mechanism aligns the reference current in the center of the window according to the actual current distribution of the memory cells for each chip measured during the test process. The other mechanism reduces the offset of the sense amplifier.

With these adjustments, faster read speed is achieved. Furthermore, in conventional configurations, there is large parasitic capacitance in the circuits used to control the voltage of the bitline so it does not rise too high during read operations. This slows the reading process, so a Cascode connection scheme (Note 1) is introduced in this circuit to reduce parasitic capacitance and speed up reading.

Thanks to these advances, Renesas can achieve the world?s fastest random read access time of 4.2 ns. Even taking into consideration the setup time of the interface circuit that receives the MRAM output data, the company can realize the random read operation at frequencies in excess of 200 MHz.