By Targeted News Service
ALEXANDRIA, Va., Sept. 23 -- STMicroelectronics, Coppell, Texas, has been assigned a patent (9,450,618) developed by three co-inventors for "max-Log-MAP equivalence log likelihood ratio generation soft Viterbi architecture system and method." The co-inventors are Sivagnanam Parthasarathy, Carlsbad, California, Lun Bin Huang, San Diego, and Alessandro Risso, San Diego.
The patent application was filed on Feb. 27, 2014 (14/192,674). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=9,450,618.PN.&OS=PN/9,450,618&RS=PN/9,450,618
Written by Deviprasad Jena; edited by Jaya Anand.
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