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4-Traders Homepage  >  Equities  >  TAIWAN STOCK EXCHANGE  >  United Microelectronics Corp.    2303   TW0002303005

UNITED MICROELECTRONICS CORP. (2303)
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United Microelectronics : Patent Issued for Semiconductor Structure and Method for Fabricating the Same (USPTO 9966382)

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05/17/2018 | 11:21pm CEST

By a News Reporter-Staff News Editor at Investment Weekly News -- United Microelectronics Corp. (Hsinchu, TW) has been issued patent number 9966382, according to news reporting originating out of Alexandria, Virginia, by VerticalNews editors.

The patent's inventors are Wang, Chia-Wen (Tainan, TW); Lee, Hsiang-Chen (Kaohsiung, TW); Hsu, Wen-Peng (New Taipei, TW); Li, Kuo-Lung (Yunlin County, TW); Chen, Meng-Chun (Kaohsiung, TW); Liu, Zi-Jun (Kaohsiung, TW); Shih, Ping-Chia (Tainan, TW).

This patent was filed on August 16, 2016 and was published online on May 8, 2018.

From the background information supplied by the inventors, news correspondents obtained the following quote: "Field of Invention

"This invention relates to a semiconductor process, and particularly relates to a method for fabricating a semiconductor structure, and to a semiconductor structure and a semiconductor device fabricated with the method.

"Description of Related Art

"A non-volatile memory (NVM) device usually has lightly doped drain (LDD) regions beside the gate. Conventionally, the LDD implantation is performed after the gate is formed but before the process of the ONO spacer, so that the distance between the opposite LDD regions is smaller. As a result, problems such as the short-channel effect are caused, and the chip probe (CP) yield and so on is lowered."

Supplementing the background information on this patent, VerticalNews reporters also obtained the inventors' summary information for this patent: "Accordingly, this invention provides a method for fabricating a semiconductor structure, which allows the LDD regions to be 'pulled back' increasing the distance between the opposite LDD regions.

"This invention also provides a semiconductor structure that is fabricated with the above method of this invention.

"This invention also provides a method for fabricating a semiconductor device, which can be considered as a core part of the above method of this invention.

"The method for fabricating a semiconductor structure of this invention is described as follows. A first gate of a first device and a second gate of a second device are formed over a semiconductor substrate. First LDD regions are formed in the substrate beside the first gate using the first gate as a mask. A conformal layer is formed covering the first gate, the second gate and the substrate, wherein the conformal layer has sidewall portions on the sidewalls of the second gate. Second LDD regions are formed in the substrate beside the second gate using the second gate and the sidewall portions of the conformal layer as a mask.

"The semiconductor structure includes a first device and a second device. The first device includes a first gate, and first LDD regions beside the first gate. The second device includes a second gate, and second LDD regions beside the second gate. The distance between the second gate and each second LDD region is greater than the distance between the first gate and each first LDD region.

"In an embodiment, the first device comprises a logic device and the second device comprises an NVM device. In such case, the conformal layer may comprise a first silicon oxide (SiO.sub.2) layer for forming the first oxide layer of an ONO spacer, or may alternatively comprise a first SiO.sub.2 layer and an SiN layer thereon, which are for forming the first oxide layer and the nitride layer of an ONO spacer, respectively.

"When the conformal layer comprises the first SiO.sub.2 layer for forming the first oxide layer of the ONO spacer, the inner border of each second LDD region of the NVM device is positioned between the sidewall of the second gate and the sidewall of the first SiO.sub.2 layer, while each first LDD region of the logic device overlaps with the first gate.

"The method for fabricating a semiconductor device of this invention is described as follows. A gate is formed over a semiconductor substrate. A conformal layer is formed covering the gate and the substrate, wherein the conformal layer has sidewall portions on the sidewalls of the gate. LDD regions are then formed in the substrate using the gate and the sidewall portions of the conformal layer as a mask.

"In an embodiment, the semiconductor device comprises an NVM device, and the conformal layer may comprise the aforementioned.

"Since the sidewall portions of the conformal layer also serve as a mask in the LDD implantation of the NVM device in this invention, the opposite LDD regions beside the gate of the NVM device can be pulled back so that their distance is increased and problems such as the short-channel effect are avoided.

"In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, a preferred embodiment accompanied with figures is described in detail below."

For the URL and additional information on this patent, see: Wang, Chia-Wen; Lee, Hsiang-Chen; Hsu, Wen-Peng; Li, Kuo-Lung; Chen, Meng-Chun; Liu, Zi-Jun; Shih, Ping-Chia. Semiconductor Structure and Method for Fabricating the Same. U.S. Patent Number 9966382, filed August 16, 2016, and published online on May 8, 2018. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=9966382.PN.&OS=PN/9966382RS=PN/9966382

Keywords for this news article include: Asia, Taiwan, Business, Semiconductor, United Microelectronics Corp.

Our reports deliver fact-based news of research and discoveries from around the world. Copyright 2018, NewsRx LLC

(c) 2018 NewsRx LLC, source Business Newsletters

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Financials ( TWD)
Sales 2018 155 B
EBIT 2018 5 948 M
Net income 2018 8 809 M
Finance 2018 579 M
Yield 2018 3,93%
P/E ratio 2018 20,96
P/E ratio 2019 16,82
EV / Sales 2018 1,31x
EV / Sales 2019 1,11x
Capitalization 205 B
Income Statement Evolution
Consensus
Sell
Buy
Mean consensus HOLD
Number of Analysts 21
Average target price 13,6  TWD
Spread / Average Target -16%
EPS Revisions
Managers
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Shan Chieh Chien Co-President & Director
Jason Wang Co-President
Chi Tung Liu Head-Finance & Head-Accounting
Chiung Lang Liu Independent Director
Chen Feng Huang Independent Director
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