TSMC unveiled its newest semiconductor process, advanced packaging, and 3D IC technologies for powering the next generation of AI innovations with silicon leadership at the Company's 2024 North America Technology Symposium. TSMC debuted the TSMC A16TM technology, featuring leading nanosheet transistors with innovative backside power rail solution for production in 2026, bringing greatly improved logic density and performance. TSMC also introduced its System-on-Wafer (TSMC-SoW??) technology, an innovative solution to bring revolutionary performance to the wafer level in addressing the future AI requirements for hyperscaler datacenters.

This year marks the 30th anniversary of TSMC's North America Technology Symposium, and more than 2,000 attended the event, growing from less than 100 attendees 30 years ago. The North America Technology Symposium in Santaara, California kicks off TSMC Technology Symposiums around the world in the coming months. The symposium also features an "Innovation Zone," designed to highlight the technology achievements of emerging start-up customers.

TSMC NanoFlexTM Innovation for Nanosheet Transistors: TSMC's upcoming N2 technology will come with TSMC NanoFlex, the company's next breakthrough in design-technology co-optimization. TSMC NanoFlex provides designers with flexibility in N2 standard cells, the basic building blocks of chip design, with short cells emphasizing small area and greater power efficiency, and tall cells maximizing performance. Customers are able to optimize the combination of short and tall cells within the same design block, tuning their designs to reach the optimal power, performance, and area tradeoffs for their application.

N4C Technology: Bringing TSMC's advanced technology to a broader range of applications, TSMC announced N4C, an extension of N4P technology with up to 8.5% die cost reduction and low adoption effort, scheduled for volume production in 2025. N4C offers area-efficient foundation IP and design rules that are fully compatible with the widely-adopted N4P, with better yield from die size reduction, providing a cost-effective option for value-tier products to migrate to the next advanced technology node from TSMC. CoWoS®?, SoIC, and System-on-Wafer®?): TSMC's Chip on Wafer on Substrate (CoWoS®?) has been a key enabler for the AI revolution by allowing customers to pack more processor cores and high-bandwidth memory (HBM) stacks side by side on one interposer.

At the same time, System on Integrated Chips (SoIC) has established itself as the leading solution for 3D chip stacking, and customers are increasingly pairing CoWoS with SoIC and other components for the ultimate system-in-package (SiP) integration. With System-on-Wafer, TSMC is providing a revolutionary new option to enable a large array of dies on a 300mm wafer, offering more compute power while occupying far less data center space and boosting performance per watt by orders of magnitude. COUPE uses SoIC-X chip stacking technology to stack an electrical die on top of a photonic die, offering the lowest impedance at the die-to-die interface and higher energy efficiency than conventional stacking methods.

TSMC plans to qualify COUPE for small form factor pluggables in 2025, followed by integration into CoWoS packaging as co-packaged optics (CPO) in 2026, bringing optical connections directly into the package. Automotive Advanced Packaging: After introducing the N3AE "Auto Early" process in 2023, TSMC continues to serve automotive customers' needs for greater computing power that meets the safety and quality demands of theway by integrating advanced packaging. TSMC is developing InFO-oS and CoWoS-R solutions for applications such as advanced driver assistance systems (ADAS), vehicle control, and vehicle control, and vehicle central computers, targeting AEC-Q100 Grade 2 qualification by fourth quarter of 2025.